Adaptive Clock Management in Hardware Emulation
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Solution Overview
Problem
In hardware emulation, there is a challenge in managing clock signals to accommodate the conflicting speed requirements between emulator resources and dynamic targets, leading to inefficiencies and potential timeout errors due to temporary suspension of clock signals.
Innovation Solution
The implementation of adaptive clock management techniques, which involve generating a clock suspension request signal based on emulator resource activity status and a clock suspension allowance signal based on dynamic target speed constraints, allowing for controlled temporary suspensions of design clock signals to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are temporarily suspended to accommodate software environment communication and hardware resource access, then the emulator can synchronize with slower targets and perform necessary operations, but the emulation speed decreases and productivity is reduced
Solution Approach 1:
The patent implements dynamic clock management by making the clock signal state (running or suspended) variable and adaptive rather than fixed. The clock controller dynamically transitions the design clock signal between active and suspended states based on real-time conditions such as buffer status and target readiness, allowing the system to optimize between synchronization reliability and emulation speed continuously during operation.
Solution Approach 2:
The patent employs feedback mechanisms where the clock controller monitors the status of data buffers and target readiness signals, then uses this feedback information to make informed decisions about clock suspension. The system continuously evaluates whether suspension is necessary based on current system state, creating a closed-loop control system that balances synchronization needs against productivity requirements.
2Loss of information
If clock signals are suspended frequently to maintain synchronization, then data loss is minimized, but timeout errors increase and system performance deteriorates
Solution Approach 1:
The patent prepares for potential data loss by implementing preliminary checks of buffer status and target readiness before clock suspension occurs. The system proactively manages data buffering and prepares target systems in advance to minimize the impact of upcoming clock suspensions, reducing both data loss and timeout errors through anticipatory control measures.
3Productivity
If the emulator operates at high speed continuously, then productivity is maximized, but synchronization with slower targets becomes impossible and data loss occurs
Solution Approach 1:
The patent implements periodic clock suspension cycles rather than continuous operation. The clock signal alternates between running and suspended states in periodic intervals, allowing the emulator to maintain high-speed operation during active periods while periodically synchronizing with slower targets during suspension periods. This periodic rhythm balances productivity maximization with data loss prevention.
Data Source
AI summary
Aspects of the invention relate to techniques for adaptive clock management in emulation. A clock suspension request signal, indicating when a suspension of design clock signals in an emulator is needed, is generated based on activity status information of the emulator with one or more emulator resources such as software environment. A clock suspension allowance signal, indicating whether a suspension of design clock signals is permitted considering dynamic targets in the emulator, is generated based on slack information related to one or more clock signals associated with one or more dynamic targets of the emulator. Based on the clock suspension request signal and the clock suspension allowance signal, a clock suspension signal is generated for enabling temporary design clock suspensions.