Adaptive Clock Mismatch Compensation Symbol Insertion
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Solution Overview
Problem
Conventional interconnect interfaces waste bandwidth by fixing the rate of insertion of clock mismatch compensation symbols at a worst-case scenario, even when the clock frequency mismatch is less severe, leading to unnecessary transmission of skip ordered sets.
Innovation Solution
Adaptive adjustment of the rate of insertion of clock mismatch compensation symbols based on real-time measurement of the clock frequency mismatch between the transmit-side and receive-side clocks, allowing for dynamic reduction or elimination of unnecessary skip ordered sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the rate of insertion of clock mismatch compensation symbols is fixed at a worst-case scenario, then buffer underflow is prevented, but bandwidth is wasted
Solution Approach 1:
The patent implements dynamic adjustment of the skip ordered set insertion rate based on real-time measurement of actual clock frequency mismatch. The system transitions from a static fixed-rate insertion approach to a dynamic adaptive approach where the insertion rate is continuously adjusted to match the actual mismatch conditions, thereby preventing buffer underflow while minimizing bandwidth waste.
Solution Approach 2:
The system incorporates feedback mechanisms by measuring the actual clock frequency mismatch between transmit and receive sides and using this measurement to adjust the skip ordered set insertion rate. This closed-loop control ensures that the insertion rate responds to actual conditions rather than relying on predetermined worst-case assumptions.
2Reliability
If skip ordered sets are inserted at a fixed worst-case rate, then clock frequency mismatch is compensated, but interconnect bandwidth is reduced
Solution Approach 1:
The patent makes the skip ordered set insertion rate dynamic by adjusting it according to the measured actual clock frequency mismatch. This allows the system to maintain reliable clock synchronization while maximizing interconnect bandwidth utilization by inserting only the necessary compensation symbols.
Solution Approach 2:
The system changes the insertion rate parameter of skip ordered sets based on measured clock frequency mismatch conditions. By adjusting this parameter dynamically rather than fixing it at a worst-case value, the system achieves both reliable clock mismatch compensation and optimized bandwidth usage.
3Reliability
If clock mismatch compensation symbols are transmitted continuously, then receiver buffer underflow is prevented, but data transmission efficiency is reduced
Solution Approach 1:
The patent implements dynamic control of skip ordered set transmission based on actual clock mismatch measurements. The system adjusts the transmission rate to match actual needs, preventing receiver buffer underflow while maintaining high data transmission efficiency by avoiding unnecessary compensation symbol transmission.
Solution Approach 2:
Instead of continuously transmitting skip ordered sets at a fixed worst-case rate, the system transmits them at the minimum necessary rate based on actual measured mismatch conditions. This partial action approach prevents buffer underflow while minimizing the impact on data transmission efficiency.
Data Source
AI summary
A transmitting interconnect interface inserts clock mismatch compensation symbols into a transmitted data stream so as to allow the receiving interconnect interface to compensate for clock frequency mismatch between transmit-side and receive-side clocks. The transmitting interconnect interface adjusts the rate of insertion of these symbols based on a determination of the clock frequency mismatch. The transmitting interconnect interface can incrementally adjust the insertion rate to change substantially proportionally with changes in the clock frequency mismatch. Alternatively, the transmitting interconnect interface can set the insertion rate to one of two levels. By adapting the insertion rate to the current measured clock frequency mismatch, the bandwidth penalty incurred by transmitting clock mismatch compensation symbols in excess of that necessary to permit receiver clock tolerance compensation can be reduced, thereby permitting more transmit bandwidth to be used for transmitting data.