Adaptive Clock Frequency Circuit for Power Supply Noise Timing Margin
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Solution Overview
Problem
The increase in electric current consumption by integrated circuits leads to power supply noise, causing voltage drops and delays, necessitating large margins that hinder frequency enhancement and power reduction in LSIs.
Innovation Solution
A clock frequency adjusting circuit with a detection circuit and a clock frequency controlling circuit that synchronizes noise detection with clock selection, allowing for immediate frequency adjustment upon noise detection, reducing synchronization delays and margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a margin is provided to the timing of an operation in an internal circuit to absorb increased delay time caused by power supply noise, then the reliability is improved, but the frequency of the LSI cannot be enhanced and consumed electric power cannot be lowered
Solution Approach 1:
The patent applies dynamics by making the timing margin adaptive rather than static. The noise detection circuit dynamically adjusts the effective margin by detecting power supply noise and controlling the clock selection circuit to switch between different clock frequencies, thereby optimizing both reliability and frequency performance under varying noise conditions.
Solution Approach 2:
The patent changes the clock frequency parameter in response to detected power supply noise. The clock selection circuit switches between multiple clock frequencies based on noise detection results, allowing the system to maintain timing margins when needed while operating at higher frequencies when the power supply is stable, thus resolving the contradiction between reliability and productivity.
2Measurement precision
If a noise detection voltage higher than the operation limit voltage is used to detect power supply noise, then the detection accuracy is improved, but the delay time from noise detection to clock frequency lowering increases
Solution Approach 1:
The patent applies preliminary action by providing multiple clock frequencies in advance to the clock selection circuit. When noise is detected, the system can immediately switch to a pre-prepared lower frequency without calculation or generation delay, significantly reducing the response time while maintaining accurate noise detection through the higher noise detection voltage.
3Reliability
If the clock frequency is lowered when power supply noise is detected, then the reliability is improved, but the processing performance deteriorates
Solution Approach 1:
The patent makes the clock frequency dynamic rather than fixed. The system continuously monitors power supply noise and adjusts the clock frequency in real-time, maintaining high frequencies for optimal performance when the power supply is stable and switching to lower frequencies only when necessary to maintain reliability under noise conditions.
Solution Approach 2:
The patent changes the clock frequency parameter based on power supply conditions. By switching between multiple predefined clock frequencies according to noise detection results, the system optimizes the balance between reliability and processing performance, operating at high frequencies when possible and lowering frequency only when noise threatens operational stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and maintains high processing performance by minimizing frequency adjustments due to power supply noise, enabling efficient operation at lower voltages.
Implementation Method 1
a first delay circuit that outputs a first delayed clock signal obtained by delaying the first clock signal according to an operation voltage of the integrated circuit
Implementation Method 2
a second delay circuit that outputs a second delayed clock signal obtained by delaying the first clock signal according to a threshold voltage lower than the operation voltage
Implementation Method 3
a detection signal output circuit that outputs the detection signal based on a result of comparing a phase of the first delayed clock signal and a phase of the second delayed clock signal
Data Source
AI summary
An adjusting circuit includes: a detection circuit outputting a detection signal indicative of whether a noise occurs in electric power inputted into an integrated circuit operating in synchronization with a clock signal; and a controlling circuit outputting to the integrated circuit a first clock signal having a first frequency, or a second clock signal having a second frequency lower than the first frequency when the detection signal indicates the noise occurs. The detection circuit includes a first circuit outputting a first delayed clock signal obtained by delaying the first clock signal according to an operation voltage of the integrated circuit, a second circuit outputting a second delayed clock signal obtained by delaying the first clock signal according to a threshold voltage lower than the operation voltage, and an output circuit outputting the detection signal based on a result of comparing phases of the first and second delayed clock signals.