Adaptive Clock Circuit With Phase Selection for Wide-Range Frequency Scaling
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Solution Overview
Problem
Existing clock signal circuits sacrifice precision for area cost and have a narrow frequency regulating range, with existing methods like DLL and PLL being inefficient in terms of response time, power consumption, and adaptability.
Innovation Solution
A two-way adaptive clocking circuit with a phase clock generating module, phase clock selecting module, adaptive clock stretching or compressing amount regulating circuit, and control module, which uses a double-delay-line structure and transition detectors to fine-tune clock signals within a wide frequency range based on real-time delay information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DLL-based clock stretching method is used, then clock frequency can be rapidly changed, but response time is long, power consumption is high, and area cost is high
Solution Approach 1:
The clock stretching function is segmented into multiple independent phase clocks (first phase clock, second phase clock, third phase clock, fourth phase clock) with different phase differences. This allows the system to select appropriate phase clocks based on timing requirements, achieving rapid clock stretching without the long response time of traditional DLL-based methods. Each phase clock can be independently activated to provide immediate frequency adjustment.
Solution Approach 2:
Multiple phase clocks with predetermined phase differences are generated in advance and stored in the clock output circuit. When clock stretching is needed, the system simply switches to a pre-prepared phase clock with the appropriate phase difference, eliminating the need for real-time phase adjustment and reducing response time significantly.
2Speed
If integer multiple frequency division is performed on the clock, then frequency reduction can be realized, but the frequency of the chip is greatly reduced and performance is greatly reduced
Solution Approach 1:
Instead of uniformly reducing the entire clock frequency through integer multiple division, the invention applies localized phase adjustment only to the specific clock paths that require stretching. The phase clock generating module creates multiple phase clocks with different phase differences, allowing selective stretching of only the necessary clock signals while maintaining high frequency for other parts of the chip, thus preserving overall performance.
3Reliability
If sufficient timing margin is reserved in the circuit design process, then the chip can work normally in the worst case, but performance and power consumption are wasted
Solution Approach 1:
The invention replaces static timing margin reservation with dynamic clock frequency adjustment. The clock output circuit dynamically selects different phase clocks based on real-time timing requirements, allowing the system to operate at high performance when timing conditions are good and automatically stretch the clock when timing violations occur. This eliminates the need for conservative static timing margins while maintaining reliability, thereby reducing unnecessary power consumption.
Solution Approach 2:
The timing detection module continuously monitors the timing status of the chip and provides feedback to the clock output circuit. Based on this feedback, the system automatically adjusts the clock phase and frequency to maintain proper timing without requiring excessive static timing margins. This closed-loop control ensures reliable operation while minimizing power consumption by avoiding unnecessary performance reduction.
4Speed
If PLL dynamic configuration method is used, then fast frequency regulation can be realized, but design complexity is high and universality is low
Solution Approach 1:
The phase clock generating module is designed to generate multiple phase clocks with different phase differences using a unified structure. This multi-functional module can serve various clock stretching requirements without requiring different PLL configurations for different scenarios. The same basic circuitry can adapt to different frequency regulation needs by selecting appropriate phase clocks, reducing design complexity and improving universality compared to PLL-based solutions.
Data Source
AI summary
A two-way adaptive clock circuit supporting a wide frequency range is composed of a phase clock generating module, a phase clock selecting module, an adaptive clock stretching or compressing amount regulating circuit module and a control module. The adaptive clock stretching or compressing amount regulating circuit module can monitor delay information of a critical path in a chip in real time and feed the information back into the control module. After receiving a clock stretching or compressing enable signal and a stretching or compressing scale signal, the control module selects a target phase clock from clocks generated by the phase clock generating module to rapidly regulate an adaptive clock in a current cycle. The present invention is applied to an adaptive voltage frequency regulating circuit based on on-line time sequence monitoring.