Adaptive Clock Subsystem for Seamless Power Mode Switching
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Solution Overview
Problem
Conventional clock signal management methods for microcontrollers face challenges in seamlessly transitioning between high and low power modes, leading to discontinuity and latency, and require either multiple oscillators or software reconfiguration, which are costly or inefficient.
Innovation Solution
A clock subsystem with an oscillator capable of generating multiple frequencies, controlled by a controller that determines the desired frequency based on power mode and ADC input, allowing for adaptive clock management without dedicated oscillators or software intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple oscillators are used to provide different clock signals for high-power and low-power modes, then seamless operation and continuous clock signal are achieved, but device cost and power consumption increase
Solution Approach 1:
The patent applies multi-functionality by enabling a single oscillator to serve multiple purposes: generating clock signals for both high-power mode (with ADC at full sampling rate) and low-power mode (with ADC at reduced sampling rate). The oscillator dynamically adjusts its frequency based on power mode requirements, eliminating the need for separate dedicated oscillators while maintaining continuous operation.
Solution Approach 2:
The patent merges the functions of multiple oscillators into a single oscillator unit. By combining the high-power mode clock generation and low-power mode clock generation into one oscillator, the system reduces component count and complexity while ensuring seamless transitions between power modes through dynamic frequency adjustment.
2Adaptability or versatility
If software reconfiguration is used to adjust peripheral sampling rates during mode transitions, then flexibility is achieved, but functional discontinuity and latency occur
Solution Approach 1:
The patent applies preliminary action by pre-configuring the oscillator to dynamically adjust its frequency in anticipation of power mode transitions. The oscillator is designed to automatically switch between frequency ranges (first frequency for high-power mode, second frequency for low-power mode) based on system state, eliminating the need for software reconfiguration steps and reducing transition latency.
Solution Approach 2:
The patent implements dynamics by making the oscillator frequency adjustable and responsive to power mode changes. The oscillator transitions from a static frequency source to a dynamic one that can switch between first frequency and second frequency based on real-time system requirements, enabling seamless mode transitions without software intervention.
3Use of energy by moving object
If the peripheral operates below its usual sampling rate to use a low-frequency clock signal, then power consumption is reduced, but the peripheral does not function properly or efficiently
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the oscillator frequency parameter based on power mode. During low-power mode, the oscillator operates at a second frequency optimized for reduced power consumption while still providing sufficient sampling rate for ADC functionality. During high-power mode, it switches to a first frequency that enables full ADC performance, thus optimizing both power efficiency and productivity according to system state.
Data Source
AI summary
Various embodiments disclosed herein relate to adaptive clock signal management, and more specifically to generating a clock signal at desired frequencies based on inputs to a clock subsystem for peripheral use. A clock subsystem is provided herein that comprises an oscillator configured to provide a clock signal at either a first frequency or a second frequency, and a controller coupled to the oscillator and configured to perform various functions. The controller can be configured to determine a desired frequency of the clock signal based on a state of each input of multiple inputs, wherein the multiple inputs comprise a power mode input and an analog-to-digital converter input, and provide a signal to the oscillator to produce the clock signal at the desired frequency.