Adaptive Clock Recovery Circuit for High-Drift Serial Links
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Solution Overview
Problem
Local devices often experience intolerable clock signal drifts exceeding 1,000 ppm due to using inexpensive or poorly performing reference clock sources, which fail to meet the tighter tolerance requirements of serial communication protocols like SATA, which operate at higher frequencies.
Innovation Solution
The proposed solution involves a circuit with a phase locked loop, offset adjustment circuit, phase interpolators, clock recovery circuit, frequency detector, and transmitter that adjust the local clock signal to align with the host clock signal, using timing information to calculate and correct phase and frequency offsets, thereby generating a transmit clock signal that meets the required tolerance limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If inexpensive reference clock sources are used, then cost is reduced, but clock drift exceeds acceptable tolerance limits
Solution Approach 1:
The patent introduces a phase-locked loop (PLL) as an intermediary component between the inexpensive reference clock source and the serial communication interface. The PLL receives the low-cost reference clock and generates a derived clock signal with significantly reduced drift (within 350 ppm tolerance), effectively mediating between the cheap reference source and the stringent protocol requirements.
Solution Approach 2:
The system dynamically adjusts clock parameters by using a fractional-N PLL that can change the output frequency in fine increments. The offset adjustment circuit modifies the PLL's division ratio and phase offset parameters to precisely control the output clock frequency, transforming the poor quality reference clock into a compliant communication clock.
2Speed
If serial communication protocols operate at higher frequencies, then data transmission speed is improved, but clock drift tolerance requirements become tighter
Solution Approach 1:
The patent implements a feedback mechanism where the offset adjustment circuit continuously monitors the PLL's output clock signal and adjusts control parameters to maintain frequency accuracy. This closed-loop feedback ensures that even at high serial communication speeds, the clock drift remains within the tight 350 ppm tolerance required by SATA protocols.
Solution Approach 2:
The system uses a dynamic fractional-N PLL that can adaptively adjust its division ratio and phase offset in real-time. This dynamic capability allows the system to maintain precise clock synchronization at high data rates, where static frequency division would be insufficient to meet the tight tolerance requirements.
3Stability of the object's composition
If a phase locked loop is used to generate local clock signal, then clock signal stability is improved, but additional circuit components are required
Solution Approach 1:
The patent designs the offset adjustment circuit to perform multiple functions: it adjusts the PLL's division ratio, controls phase offset, and generates control signals for the phase interpolator. This multi-functional approach consolidates several clock adjustment operations into a single circuit block, reducing overall system complexity while maintaining clock signal stability.
Solution Approach 2:
The system merges the reference clock input, PLL frequency synthesis, phase interpolation, and offset adjustment into an integrated clock recovery circuit. By combining these functions that could be separate modules into a unified structure, the patent achieves clock signal stability without proportionally increasing device complexity.
Data Source
AI summary
Circuits and methods are provided for adjusting a frequency of a local clock signal in approximating a frequency of a host clock signal. A phase locked loop generates a local clock signal having a first phase and a first frequency. An offset adjustment circuit receives timing information relating the local clock signal to an incoming data signal and calculates a phase offset and a frequency offset indicative of adjustments to be made to the local clock signal. A first phase interpolator generates a receive clock signal from the local clock signal, the receive clock signal having a second phase and a second frequency responsive to the phase and frequency offsets. A second phase interpolator generates a transmit clock signal from the local clock signal having a third frequency responsive to the frequency offset.