Adaptive Clock Recovery Circuit for Wide-Band Jitter Control
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Solution Overview
Problem
High resolution display devices face challenges in maintaining stable clock and data recovery due to varying frequency bands, leading to significant jitter in clock signals, especially when operating in low speed regions.
Innovation Solution
A clock and data recovery circuit that includes an automatic frequency controller and a voltage-controlled oscillator, which adjusts parameters based on detected frequency bands to synchronize clock signals and reduce jitter across a wide range of frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed parameter configuration is used in the clock and data recovery circuit, then the circuit structure remains simple, but jitter characteristics deteriorate in low speed regions
Solution Approach 1:
The patent implements dynamic parameter adjustment in the clock and data recovery circuit by detecting the frequency band of the input clock signal and automatically adjusting internal parameters (such as charge pump current, loop filter coefficients, or VCO control ranges) to optimize jitter characteristics for each frequency band, transforming a static circuit into an adaptive system that maintains high reliability across varying operating conditions
Solution Approach 2:
The patent changes operational parameters of the clock and data recovery circuit based on detected frequency bands, adjusting key parameters such as charge pump current magnitude, loop filter time constants, or voltage-controlled oscillator gain to match optimal values for different frequency ranges, thereby resolving the contradiction between simple structure and reliable performance
2Adaptability or versatility
If the clock and data recovery circuit operates across a wide frequency range, then adaptability improves, but jitter control worsens in specific frequency bands
Solution Approach 1:
The patent segments the wide frequency range into multiple discrete frequency bands and implements band-specific parameter configurations, allowing the circuit to optimize jitter control for each segment while maintaining overall wide adaptability, effectively dividing the operational spectrum into manageable zones with tailored characteristics
Solution Approach 2:
The patent employs dynamic parameter adjustment that automatically adapts to the detected frequency band, enabling the circuit to maintain optimal jitter characteristics across the entire wide frequency range by continuously adjusting parameters based on real-time frequency detection, thus achieving both wide adaptability and reliable jitter control
3Reliability
If parameter adjustment is implemented for different frequency bands, then jitter characteristics improve, but device complexity increases
Solution Approach 1:
The patent implements a self-service mechanism where the clock and data recovery circuit automatically detects its own operating frequency band and adjusts its internal parameters without external intervention, using built-in frequency detection and control logic that eliminates the need for manual configuration or complex external control systems
Solution Approach 2:
The patent incorporates feedback mechanisms where the output of the clock and data recovery circuit is monitored and fed back to automatically adjust parameters for optimal jitter performance, creating a closed-loop system that self-optimizes based on actual operating conditions rather than requiring complex open-loop control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures stable clock signal recovery across varying frequency bands, optimizing performance in both high and low speed operation regions, thereby maintaining uniform jitter characteristics.
Implementation Method 1
a voltage-controlled oscillator for outputting a second internal clock signal according to the frequency band, and outputting a third internal clock signal based on a control voltage
Implementation Method 2
a charge pump for adjusting a control voltage to the voltage-controlled oscillator based on phase difference between the reference clock signal and the second internal clock signal
Implementation Method 3
a loop filter for outputting the control voltage to the voltage-controlled oscillator based on the current output by the charge pump
Data Source
AI summary
A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.