Adaptive Clock Circuit for RF Interference Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Computer platforms face performance degradation due to radio frequency interference (RFI) from sources like Wi-Fi and cellphone signals, leading to issues such as display flickering and system crashes, and existing mitigation methods like shielding and phase-locked loops (PLLs) increase costs and power consumption.
Innovation Solution
An adaptive RFI mitigation architecture that engages mitigation circuitry only when necessary, using an adaptive clock generator with a low-pass filter and digital signal generators to detect and mitigate RFI by adjusting clock generation based on jitter and duty cycle monitoring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shielding and phase-locked loops (PLLs) are used to mitigate RFI, then RFI protection is improved, but cost and power consumption increase
Solution Approach 1:
The patent implements dynamic RFI mitigation by switching between single-ended and differential clock signal modes based on detected RFI conditions. The system monitors for RFI and dynamically adjusts the clock circuit operation mode, engaging differential mode (which provides better RFI rejection) only when RFI is detected, rather than operating in differential mode continuously. This dynamic adaptation resolves the contradiction by providing strong RFI protection only when needed, reducing power consumption during normal operation.
Solution Approach 2:
The patent changes the operational parameters of the clock circuit by switching between single-ended and differential signal configurations. When RFI is detected, the system changes from single-ended mode to differential mode, altering the electrical characteristics of the clock signal to achieve better RFI rejection. This parameter change allows the system to maintain reliability under RFI conditions while avoiding the continuous power overhead of differential mode operation.
2Reliability
If shielding and phase-locked loops (PLLs) are used to mitigate RFI, then RFI protection is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts only the essential RFI mitigation capability needed for the system by implementing a simplified approach that switches between single-ended and differential modes within the existing clock circuit. Rather than adding complex external shielding or full PLL-based mitigation systems, the invention extracts and utilizes the differential mode capability already present in many clock circuits, controlling it dynamically based on RFI detection. This reduces device complexity while maintaining effective RFI protection.
Solution Approach 2:
The patent makes the clock circuit multi-functional by enabling it to operate in both single-ended mode (for normal operation) and differential mode (for RFI mitigation) using the same hardware infrastructure. The system universally handles both operational modes through a single clock circuit design that can adapt its configuration, eliminating the need for separate dedicated RFI mitigation hardware and reducing overall device complexity.
3Reliability
If continuous RFI mitigation is applied, then RFI protection is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic RFI monitoring and mitigation by continuously detecting RFI conditions and switching between mitigation modes as needed. Rather than applying continuous RFI mitigation, the system periodically checks for RFI presence and engages differential mode only during periods when RFI is detected. This periodic action pattern resolves the contradiction by providing RFI protection during harmful periods while conserving power during normal operation.
Solution Approach 2:
The patent applies partial RFI mitigation by using only the necessary degree of differential mode operation to counteract detected RFI. The system monitors RFI levels and engages mitigation (differential mode) to the extent needed to maintain clock signal integrity, rather than applying excessive mitigation continuously. This partial action approach provides adequate RFI protection during interference events while avoiding unnecessary power consumption during clean operation periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces RFI impact with minimal power consumption, avoiding the need for costly shielding and complex PLLs, while maintaining optimal performance in the absence of RFI.
Implementation Method 1
a low-pass filter circuit coupled to an output terminal of the oscillator circuit
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
An apparatus includes an oscillator circuit and a low-pass filter circuit coupled to an output terminal of the oscillator circuit. The apparatus further includes a first digital signal generator coupled to at least one of an output terminal of the low-pass filter circuit and the output terminal of the oscillator circuit and a second digital signal generator coupled to at least one of the output terminal of the low-pass filter circuit and the output terminal of the oscillator circuit. The second digital signal generator generates a second digital clock signal based on a non-differential signal output of the oscillator circuit. The apparatus further includes a radio frequency interference (RFI) detection circuit coupled to the first digital signal generator and the second digital signal generator. The RFI detection circuit detects RFI associated with the non-differential signal output of the oscillator circuit.