Adaptive Circuit Clock Generation Using Delayed Signal Broadening
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuits, power fluctuations lead to timing errors due to unmet timing requirements, and existing solutions like phase-locked loops (PLLs) are slow in adaptive adjustment, while using two PLLs to generate different clock frequencies results in resource wastage.
Innovation Solution
An apparatus and method that generate a circuit clock signal by buffering, delaying, and broadening the original clock signal to produce a lower frequency broadened clock signal, which can be dynamically selected to adapt to power fluctuations, allowing for rapid clock adjustment and preventing timing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase-locked loops (PLLs) are used to adjust clock frequency adaptively, then timing errors can be avoided, but the adjustment speed is slow
Solution Approach 1:
The patent pre-generates multiple delayed clock signals with different delays (first delay, second delay, etc.) before they are needed. When power fluctuations occur, the controller can immediately select from these pre-prepared signals without waiting for generation or adjustment, thus achieving rapid adaptation while preventing timing errors.
2Speed
If two PLLs are used to generate different clock frequencies for rapid adjustment, then adjustment speed is improved, but device complexity and resource consumption increase
Solution Approach 1:
The patent segments a single clock signal into multiple delayed versions (first delayed clock signal, second delayed clock signal, etc.) with different delay amounts. This allows the system to have multiple clock frequency options from one original clock signal, avoiding the need for multiple PLLs while maintaining rapid adjustment capability.
Solution Approach 2:
A single clock buffer unit is designed to perform multiple functions: it can buffer the original clock signal, generate multiple delayed clock signals with different delays, and provide these signals for selection based on power conditions. This multi-functional design eliminates the need for separate PLL circuits for different frequency requirements.
3Reliability
If clock frequency is reduced to adapt to power fluctuations, then timing errors are prevented, but circuit performance decreases
Solution Approach 1:
The patent implements dynamic clock frequency selection by monitoring real-time power fluctuations and automatically selecting from multiple pre-generated delayed clock signals with different frequencies. This dynamic adaptation allows the circuit to use lower frequencies only when necessary (during power fluctuations) while maintaining higher frequencies during normal operation, thus preventing timing errors without permanently degrading circuit performance.
Data Source
AI summary
Embodiments of the present disclosure provide an apparatus and a method for generating a circuit clock signal. The apparatus comprises: a clock buffer configured to buffer an original clock signal to obtain a buffered clock signal; a clock delay unit configured to delay the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being respectively delayed by different amounts of time relative to the original clock signal; a broadened clock generator configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than that of the original clock signal; and a clock selector configured to select one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on a selection signal.