Adaptive Clock Rate Control for Synchronized Signal Flow
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Solution Overview
Problem
Conventional signal transmission and reception architectures in electronic devices often result in incorrect behavior or data loss due to improper synchronization between signal transmitting and receiving circuits, as they fail to adjust transmission rates based on the receiving circuit's processing capacity.
Innovation Solution
An electronic device with a signal transmitting circuit and a signal receiving circuit that uses control circuitry to adjust clock signals based on status signals from the receiving circuit, employing programmable phase-locked loop (PLL) or delay-locked loop (DLL) circuitry to dynamically adjust clock frequencies and enable/disable clock signals, ensuring synchronized data transmission and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the signal transmitting circuit interrupts the clock signal to stop data transmission, then data loss is prevented, but transmission efficiency decreases due to discrete clock cycle interruptions
Solution Approach 1:
The patent applies dynamics by making the clock signal rate adjustable rather than fixed. The transmitting circuit dynamically changes the clock signal frequency to match the receiving circuit's processing capacity, allowing smooth rate adjustments instead of discrete on/off interruptions. This resolves the contradiction by maintaining continuous transmission (high productivity) while adapting the rate to prevent data loss (high reliability).
Solution Approach 2:
The patent changes the parameter of clock signal frequency dynamically. Instead of simply interrupting the clock signal (binary on/off), the system adjusts the clock rate continuously or in steps to match the receiving circuit's capacity. This parameter change allows the transmitting circuit to maintain transmission while preventing data loss by syncing with the receiver's processing ability.
2Productivity
If the signal transmitting circuit continues transmitting data without interruption, then transmission efficiency is maintained, but data loss occurs when the receiving circuit is not ready
Solution Approach 1:
The patent implements feedback by having the receiving circuit communicate its processing status back to the transmitting circuit. The receiving circuit provides feedback signals indicating whether it is ready to accept data, and the transmitting circuit uses this feedback to adjust its transmission rate accordingly. This resolves the contradiction by maintaining continuous transmission (high productivity) while using feedback to prevent data loss (high reliability).
Solution Approach 2:
The system dynamically adjusts the transmission rate based on real-time feedback from the receiving circuit. When the receiver is ready, transmission proceeds at high speed; when not ready, the rate is reduced or paused. This dynamic adaptation maintains overall transmission efficiency while preventing data loss.
3Reliability
If the signal transmitting circuit uses hold instructions to pause transmission, then data loss is prevented, but device complexity increases due to additional control mechanisms
Solution Approach 1:
Instead of adding complex control circuitry for hold instructions, the patent changes the approach by adjusting the clock signal frequency parameter. This is achieved through existing clock generation circuits that can vary their output frequency, avoiding the need for additional complex control mechanisms while still preventing data loss.
Solution Approach 2:
The clock generation circuit serves itself by automatically adjusting its frequency based on feedback from the receiving circuit. The system uses its own resources (the programmable clock generator) to regulate transmission, eliminating the need for separate complex control circuitry and reducing overall device complexity.
4Productivity
If the clock signal rate is dynamically adjusted based on receiving circuit capacity, then transmission efficiency improves, but device complexity increases due to programmable clock generation
Solution Approach 1:
The patent uses a programmable clock generator that serves multiple functions: it provides the clock signal for data transmission, adjusts the frequency based on processing capacity, and can be programmed through standard configuration interfaces. This multi-functionality avoids adding separate complexity while achieving dynamic rate adjustment for improved transmission efficiency.
Solution Approach 2:
The programmable clock generator is self-configuring based on feedback from the receiving circuit. It automatically adjusts its frequency without requiring external complex control logic, using its own programmable capabilities to regulate the transmission rate and improve efficiency.
Data Source
AI summary
Control circuitry and adjustable clock signal generation circuitry is provided to control the signal transmission rate for electronic devices and systems of electronic devices. The control circuitry may receive status signals indicating current clock rates of a signal transmitting and receiving circuit as well as current processing capacity from the signal receiving circuit. The control circuitry may then generate control signals which control adjustable clock signal generation circuitry. The adjustable clock signal generation circuitry may be used to adjust the rate of generated clock signals for the signal transmitting and receiving circuits which can increase or decrease the signal transmission rate between those circuits.