Adaptive Clock Modulation for Voltage Droop Timing Control
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Solution Overview
Problem
Conventional methods to mitigate voltage droops in integrated circuits often result in increased power consumption and performance loss, failing to effectively manage sudden changes in workload that cause sharp decreases in supply voltage.
Innovation Solution
An adaptive clock modulation (ACM) system that includes a delay circuit, frequency clamp, and squash controller to adjust clock frequency in response to die voltage changes, using two thresholds to distinguish between different droop events and prevent setup violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard approaches are used to mitigate voltage droops, then voltage stability is improved, but power consumption increases and device performance decreases
Solution Approach 1:
The patent implements dynamic clock frequency adjustment based on real-time voltage conditions. The clock modulation logic continuously monitors voltage droop events and adapts the clock frequency accordingly, transitioning from static to dynamic operation. This allows the system to maintain voltage stability only when necessary, reducing power consumption during normal operation.
Solution Approach 2:
The system changes the clock frequency parameter in response to voltage droop detection. By modulating the clock frequency between different states (normal, reduced, halted), the system dynamically adjusts operational parameters to balance voltage stability requirements with power consumption optimization.
2Reliability
If standard approaches are used to mitigate voltage droops, then voltage stability is improved, but device performance decreases
Solution Approach 1:
The system dynamically adjusts clock frequency based on actual voltage conditions rather than applying static performance reduction. This allows the device to maintain full performance when voltage is stable and only reduces performance when necessary to prevent functional failure, optimizing the balance between reliability and productivity.
Solution Approach 2:
The clock modulation logic uses feedback from voltage droop detection to control clock frequency adjustment. This closed-loop approach ensures performance is reduced only in response to actual voltage instability events, maintaining optimal performance during normal operation while preventing functional failure during droop events.
3Use of energy by moving object
If clock frequency is reduced to mitigate voltage droops, then power consumption decreases, but setup violations may occur during voltage recovery
Solution Approach 1:
The system applies preliminary clock stretching before voltage recovery occurs. By proactively extending the clock period in anticipation of potential setup violations during voltage rebound, the system prevents timing errors before they can occur, ensuring reliable operation during voltage transitions.
Solution Approach 2:
The clock modulation logic provides a cushioning effect by maintaining extended clock periods during voltage droop events. This creates a protective buffer that prevents setup violations during the unpredictable voltage recovery phase, ensuring timing compliance even when voltage fluctuates rapidly.
Data Source
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AI summary
Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.