Adaptive Clock Switching for Processor Voltage Droops
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Solution Overview
Problem
High-frequency supply voltage droops degrade processor performance and energy efficiency by inducing current transients, leading to reduced maximum frequency and unnecessary voltage guardbands, which are costly and inefficient, especially since droops are infrequent.
Innovation Solution
A clock module with a ring oscillator (RO) coupled to a phase-locked loop (PLL) via a multiplexor, allowing the clock to instantaneously respond to voltage droops by slowing down the frequency until the droop passes, using auto-calibration to maintain optimal performance and energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage guardbands are increased to mitigate high-frequency supply voltage droops, then processor reliability is improved, but processor performance and energy efficiency deteriorate due to reduced maximum frequency and increased power consumption
Solution Approach 1:
The patent implements a dynamic clock frequency adjustment mechanism that responds to detected voltage droops by automatically reducing clock frequency. This dynamic adaptation allows the processor to maintain reliability during droop events while avoiding the continuous performance penalty of static voltage guardbands. The system transitions between operating states based on real-time voltage conditions, optimizing the trade-off between reliability and performance.
Solution Approach 2:
The patent employs a feedback mechanism where voltage droops are detected and trigger automatic clock frequency reduction. This closed-loop control system monitors supply voltage conditions and adjusts operational parameters accordingly, allowing the processor to maintain reliability only when necessary rather than continuously sacrificing performance through static guardbands.
2Reliability
If voltage guardbands are increased to mitigate supply voltage droops, then processor reliability is improved, but energy efficiency deteriorates due to increased power consumption
Solution Approach 1:
The system dynamically adjusts clock frequency based on detected voltage droop conditions rather than maintaining a static reduced frequency state. This allows the processor to operate at full performance and efficiency during normal conditions, only reducing frequency temporarily when droops occur, thereby minimizing energy waste while maintaining reliability when needed.
Solution Approach 2:
The feedback mechanism detects voltage droops and triggers frequency reduction only during actual droop events. This on-demand response eliminates the continuous energy penalty of static guardbands, maintaining energy efficiency during normal operation while ensuring reliability when voltage droops occur.
3Reliability
If clock frequency is reduced to mitigate high-frequency supply voltage droops, then processor reliability is improved, but productivity deteriorates due to reduced maximum frequency
Solution Approach 1:
The patent implements dynamic clock frequency adjustment that responds to detected voltage droops by reducing frequency only during droop events. This temporary, condition-based frequency reduction maintains reliability during droops while preserving maximum frequency capability during normal operation, avoiding the continuous productivity loss of static frequency limiting.
Solution Approach 2:
The system takes preliminary action by detecting voltage droops and automatically reducing clock frequency before droop-induced errors can occur. This preventive mechanism ensures reliability during droop events without requiring continuous frequency reduction, thereby maintaining maximum productivity during normal operation.
4Reliability
If static clock frequency limiting is applied to mitigate supply voltage droops, then processor reliability is improved, but adaptability deteriorates due to inability to respond to varying droop conditions
Solution Approach 1:
The patent implements a dynamic clock frequency adjustment mechanism that adapts to varying droop conditions in real-time. The system responds to detected droops by reducing frequency appropriately and returns to full frequency when droops subside, providing adaptability to varying droop severity and duration while maintaining reliability during droop events.
Solution Approach 2:
The feedback mechanism enables the system to adapt to varying droop conditions by continuously monitoring voltage and adjusting frequency accordingly. This allows the processor to respond appropriately to different droop severities and durations, maintaining reliability during droops while preserving full performance capability when conditions permit.
Data Source
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AI summary
The present disclosure is directed to mitigating voltage droops. An aspect includes outputting, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module, receiving, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor, selecting, by the multiplexor, the first clock signal to output to the processor based on detecting a droop in voltage on a power supply, and selecting, by the multiplexor, the third clock signal to output to the processor based on detecting that the droop in the voltage on the power supply has passed, wherein the clock module and the processor are coupled to the power supply.