Adaptive Clocking Circuit for Low-Latency Voltage Droop Response
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Solution Overview
Problem
Existing analog PLLs do not fully exploit the benefits of Adaptive Frequency Scaling (AFS) at lower voltages and lower frequencies, leading to power wastage and impractical cooling costs due to voltage droops, which slow down clock and data signals differently.
Innovation Solution
The implementation of low latency adaptive clocking using AFS in both analog and digital PLLs, where a potentiometer senses noise on the distribution supply and injects it onto the voltage control oscillator's supply, allowing for nearly instantaneous response and reducing frequency guard-band without the need for a droop detector, enabling AFS down to lower voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high voltage margin is provided for state elements during normal operation to ensure functionality during voltage droops, then processor reliability is improved, but power consumption increases significantly
Solution Approach 1:
The patent implements dynamic voltage margin adjustment by detecting voltage droops in real-time and dynamically scaling the clock frequency in response. Instead of maintaining a static high voltage margin, the system adapts the operating parameters (frequency) based on actual voltage conditions, thereby eliminating the need for excessive power consumption during normal operation while maintaining reliability during droop events.
Solution Approach 2:
The patent employs a feedback mechanism where voltage droop detection circuits continuously monitor the power supply voltage and trigger frequency scaling responses. This closed-loop feedback system allows the processor to detect voltage droops and automatically adjust the clock frequency to maintain timing margins, replacing the open-loop approach of always providing high voltage margin with excessive power consumption.
2Reliability
If Adaptive Frequency Scaling is implemented using existing analog PLL techniques with droop detection, then processor reliability during voltage droops is improved, but latency increases due to detection and response time
Solution Approach 1:
The patent implements preliminary action by pre-configuring the frequency scaling response thresholds and adjustment parameters before voltage droops occur. The system has pre-established scaling factors and response curves that are immediately applied upon droop detection, eliminating the need for complex real-time calculations and reducing the overall response latency. The scaling logic is prepared in advance to enable instantaneous reaction to voltage droop events.
Solution Approach 2:
The patent employs skipping by implementing a streamlined droop detection and response pathway that bypasses unnecessary processing stages. Instead of following the conventional multi-stage detection and response sequence, the system uses a direct detection-to-scaling path that rushes through the critical response steps, minimizing the time between droop detection and frequency adjustment while maintaining accuracy.
3Adaptability or versatility
If existing analog PLL AFS techniques are used, then frequency scaling during voltage droops is achieved, but the system cannot fully exploit benefits at lower voltages and frequencies
Solution Approach 1:
The patent implements parameter changes by extending the frequency scaling operation to lower voltage and frequency ranges that were previously inaccessible to analog PLL AFS techniques. The system dynamically adjusts the scaling parameters and thresholds to accommodate operation at reduced voltages (e.g., down to 0.8V), enabling adaptive frequency scaling to function effectively across a broader voltage range and improving power efficiency at lower operating points.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains timing margin and reduces power consumption by allowing AFS to function at lower voltages, such as 0.8V, with minimal latency, thereby addressing the inefficiencies in existing technologies and improving processor performance under voltage droops.
Implementation Method 1
a voltage divider... is to sense noise on the second power supply rail and is to inject the sensed noise on the bias generator
Data Source
AI summary
An apparatus is provided for low latency adaptive clocking, the apparatus comprises: a first power supply rail to provide a first power; a second power supply rail to provide a second power; a third power supply rail to provide a third power; a voltage divider coupled to the first, second, and third power supply rails; a bias generator coupled to voltage divider and the third power supply rail; an oscillator coupled to the bias generator and the first supply rail; and a clock distribution network to provide an output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail.