Memory Code Rate Adaptation Using Endurance State Metrics
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Solution Overview
Problem
Existing memory sub-systems face challenges in efficiently managing code rate based on memory endurance state metrics, leading to suboptimal performance and reduced endurance of memory devices.
Innovation Solution
The proposed solution involves adjusting the code rate in a memory sub-system based on a chosen memory endurance state metric, such as program erase cycles or raw bit error rate, by using a look-up table or sample data to determine a target code rate and dynamically adjusting the ratio of user data to error correction data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If code rate is increased to maximize capacity utilization, then storage capacity is improved, but error correction capability deteriorates leading to reduced reliability
Solution Approach 1:
The patent implements dynamic code rate adjustment based on memory endurance state metrics. The system transitions from static code rate allocation to dynamic adaptation, modifying the code rate according to program erase cycle count and raw bit error rate measurements. This allows the system to optimize between capacity and reliability based on actual memory conditions rather than using a fixed code rate throughout the memory lifecycle.
Solution Approach 2:
The system changes the code rate parameter as a function of memory endurance state. By monitoring metrics such as program erase cycle count and raw bit error rate, the system adjusts the code rate parameter to match the current health state of the memory device. This parameter change enables the system to maintain optimal performance across different stages of memory degradation.
2Reliability
If over-provisioning is increased to extend memory endurance, then reliability is improved, but capacity utilization deteriorates leading to wasted storage space
Solution Approach 1:
The patent implements dynamic adjustment of the over-provisioning ratio based on memory endurance state metrics. Rather than maintaining a fixed over-provisioning ratio throughout the memory lifecycle, the system adapts the ratio according to program erase cycle count and error rate measurements. This allows the system to reduce over-provisioning when memory health is good (improving capacity utilization) and increase it when degradation is detected (maintaining reliability).
Solution Approach 2:
The system dynamically changes the over-provisioning parameter as a function of memory endurance state. By monitoring metrics such as program erase cycle count and raw bit error rate, the system adjusts the over-provisioning parameter to match current memory conditions. This parameter change enables optimal balance between endurance extension and capacity utilization at different stages of memory degradation.
3Reliability
If code rate is decreased to enhance error correction, then reliability is improved, but productivity deteriorates due to increased program erase cycles required
Solution Approach 1:
The patent implements dynamic code rate adjustment that responds to memory endurance state metrics. The system monitors program erase cycle count and raw bit error rate, then adjusts the code rate dynamically. This prevents the need for consistently low code rates (which would reduce productivity) by only increasing error correction capability when memory degradation is actually detected, thereby maintaining high productivity during the majority of the memory lifecycle.
Solution Approach 2:
The system changes the code rate parameter as a function of memory endurance state to optimize the balance between error correction and productivity. By adjusting the code rate based on program erase cycle count and raw bit error rate measurements, the system ensures that increased error correction (which would reduce productivity) is applied only when necessary, rather than maintaining a conservative low code rate throughout.
Data Source
AI summary
A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.