Adaptive Context Metadata Message for Two-Chip Storage
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Solution Overview
Problem
In flash storage devices, the inefficiency in processing multiple host commands leads to significant latency due to redundant construction, transfer, and processing of static information across descriptors, particularly in two-chip systems where the master and slave chips lack coordination in subdividing volatile memory based on descriptor types.
Innovation Solution
The introduction of an adaptive context metadata message that maps descriptor types to specific memory segments in the volatile memory, allowing the processor to store and process descriptors efficiently by identifying static information only once per descriptor type, reducing redundant operations and improving execution speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the master chip and slave chip process host commands independently without coordination, then the system can handle multiple commands, but redundant construction, transfer, and processing of static information occurs leading to significant latency
Solution Approach 1:
The volatile memory is segmented into multiple memory segments, with each segment dedicated to storing descriptors of specific types (e.g., read commands, write commands, erase commands). This segmentation allows the slave chip to quickly locate and process descriptors without searching through the entire memory space, eliminating redundant processing and reducing latency while maintaining high throughput for multiple host commands.
Solution Approach 2:
The controller pre-configures the mapping between descriptor types and memory segment indices before command execution. This preliminary setup establishes a lookup table that the slave chip can reference during command processing, eliminating the need for real-time search and comparison operations, thereby reducing processing time and latency while maintaining efficient command handling.
2Reliability
If the controller transfers complete descriptors to the slave chip for each host command, then the slave chip has all necessary information, but redundant transfer of static information increases data transmission overhead
Solution Approach 1:
The controller extracts only the essential command-specific information (such as physical address, logical page buffer address, and scatter gather list) and transfers only this variable data to the slave chip, while the static information (opcode, descriptor type) is retrieved from the pre-configured memory segment mapping. This extraction approach maintains complete command processing capability while significantly reducing the amount of data transmitted between chips.
Solution Approach 2:
Instead of transferring complete descriptor data for each command, the system creates a copy of the descriptor structure in the appropriate memory segment based on the command type. The slave chip then references this pre-positioned copy rather than receiving and processing redundant data transmissions, maintaining data completeness while reducing transmission overhead.
3Device complexity
If the slave chip processes all descriptor types uniformly, then the processing logic is simple, but the execution speed is reduced due to lack of optimization for specific descriptor types
Solution Approach 1:
Different memory segments are dedicated to specific descriptor types, allowing the slave chip to process each type with optimized local logic. The processor can quickly identify the appropriate memory segment based on the descriptor type and apply specialized processing instructions for that segment, achieving high execution speed while maintaining relatively simple overall logic through modular segment handling.
Data Source
AI summary
Aspects of a storage device including a master chip controller and a slave chip processor and memory including a plurality of memory locations are provided which allow for simplified processing of descriptors associated with host commands in the slave chip based on an adaptive context metadata message from the master chip. When the controller receives a host command, the controller in the master chip provides to the processor in the slave chip a descriptor associated with a host command, an instruction to store the descriptor in the one of the memory locations, and the adaptive context metadata message mapping a type of the descriptor to the one of the memory locations. The processor may then process the descriptor stored in the one of the memory locations based on the message, for example, by refraining from identifying certain information indicated in the descriptor. Reduced latency in command execution may thereby result.