Adaptive Core Grouping for Multi-Processor Cache Hit Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-core processor systems, the random assignment of data packets to processing cores leads to decreased performance due to frequent cache misses, as processors often need to access slower L2 caches or memory instead of faster L1 caches, which are limited in size and expensive.
Innovation Solution
A method and system where data packets are routed to processors optimized for specific tasks, with program code stored in the L1 cache, allowing for increased cache hit rates and efficient processing by dynamically assigning processors based on workload and task requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data packets are randomly assigned to processing cores, then packet distribution is simple, but cache hit rate decreases and processing performance slows down
Solution Approach 1:
The system dynamically assigns packets to processor cores based on the packet type and the processing tasks required, rather than using static random assignment. The task assignment unit selects processor cores that have the appropriate program code in their L1 caches, making the assignment adaptive and dynamic to maximize cache hit rates and processing throughput.
2Productivity
If L1 cache size is increased to improve cache hit rate, then processing speed improves, but cost increases due to expensive high-speed memory
Solution Approach 1:
Each processor core is equipped with an L1 cache that can store program code for multiple different packet processing tasks, not just a single dedicated task. This multi-functionality allows the L1 cache to serve various processing needs without requiring separate caches for each task, thereby improving cache hit rates without proportionally increasing total L1 cache capacity across the system.
Solution Approach 2:
The system pre-loads the appropriate program code into the L1 cache of selected processor cores before packets requiring those tasks arrive. The task assignment unit identifies which processor cores have the required code in their L1 caches and assigns packets to those cores, ensuring the code is already cached and ready for immediate execution, thus achieving high cache hit rates without needing large L1 caches.
3Adaptability or versatility
If processor cores access L2 cache or memory instead of L1 cache, then more program code is available, but processing speed decreases significantly
Solution Approach 1:
The task assignment unit monitors which processor cores have which program code in their L1 caches and uses this feedback information to make intelligent assignment decisions. When a packet requires specific processing tasks, the system queries which cores have the corresponding code cached and assigns the packet to one of those cores, ensuring that the required program code is already in the fast L1 cache rather than needing to be fetched from slower L2 cache or memory.
Data Source
AI summary
The present invention relates to a system, method, and non-transitory storage medium executable by one or more processors at a multi-processor system that improves load monitoring and processor-core assignments as compared to conventional approaches. A method consistent with the present invention includes a first data packet being received at a multi-processor system. After the first packet is received it may be sent to a first processor where the first processor identifies a first processing task associated with the first data packet. The first data packet may then be forwarded to a second processor that is optimized for processing the first processing task of the first data packet. The second processor may then process the first processing task of the first data packet. Program code associated with the first processing task may be stored in a level one (L1) cache at the first processor.