Adaptive CPU Core Frequency for I/O Polling Workloads

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Solution Overview

Problem

Existing storage solutions face challenges in dynamically adjusting CPU resources to match varying workloads, leading to inefficient CPU utilization and increased power consumption, while maintaining low latency and meeting performance requirements.

Innovation Solution

Implementing an inline and feedback-driven method to dynamically adjust the number of CPU cores and frequency based on real-time I/O workloads, using polling mechanisms to optimize CPU resource allocation and reduce unnecessary CPU cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If increased CPU resources are allocated to kernel device drivers to achieve high performance I/O throughput, then I/O throughput and latency are improved, but CPU resource utilization and power consumption increase

Engineering Contradiction:

ImproveI/O throughputVSAvoidCPU power consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The system dynamically adjusts the number of active CPU cores based on real-time I/O workload conditions. The management module monitors I/O operations and activates or deactivates CPU cores accordingly, transitioning from static resource allocation to dynamic adaptation, thereby optimizing both performance and power consumption

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameters of CPU resources by adjusting the number of active cores and their operational states based on I/O workload intensity. This parameter adjustment allows the system to scale CPU utilization to match actual demand, reducing wasted energy during low-workload periods

Inventive Principle:

Principle #35Parameter changes

2Productivity

If more CPU cores are used to handle I/O workloads, then I/O performance is improved, but system power consumption increases

Engineering Contradiction:

ImproveI/O performanceVSAvoidsystem power consumption

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The system employs dynamic core activation and deactivation mechanisms that respond to I/O workload conditions. The management module continuously monitors system state and adjusts the number of active CPU cores in real-time, creating a dynamic relationship between I/O performance requirements and power consumption

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system implements a feedback-driven control mechanism where the management module monitors I/O workload performance and uses this information to adjust CPU core allocation. This closed-loop feedback ensures that CPU resources are optimized based on actual I/O demands, preventing both over-provisioning and under-provisioning

Inventive Principle:

Principle #23Feedback

3Ease of operation

If traditional kernel device drivers are used with system calls and interrupt mechanisms, then I/O operations can be performed, but CPU resource utilization increases

Engineering Contradiction:

ImproveI/O operation capabilityVSAvoidCPU resource utilization

Core Design Contradiction:

Ease of operationVSUse of energy by moving object

Solution Approach 1:

The patent extracts and removes unnecessary interrupt handling mechanisms and system call overhead from the I/O processing path. By eliminating these traditional kernel driver components and replacing them with a user-space polling architecture, the system reduces CPU resource utilization while maintaining I/O operation capability

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The system replaces the traditional interrupt-driven mechanical mechanism with a polling-based software-controlled approach. This substitution eliminates the overhead associated with context switches and interrupt handling, reducing CPU resource utilization while preserving I/O functionality

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11734204B2Adaptive processor resource utilization

Publication Date: 2023.08.22 SK HYNIX NAND PRODUCT SOLUTIONS CORP

AI summary

Examples herein relate to polling for input/output transactions of a network interface or a storage device, or any peripheral device. Some examples monitor clock cycles spent checking for a presence of input/output (I/O) events and processing I/O events and monitor clock cycles spent checking for presence of I/O events without completing an I/O event. Central processing unit (CPU) core utilization can be based on clock cycles spent checking for a presence of I/O events and processing I/O events and clock cycles spent checking for presence of I/O events without completion of an I/O event. For example, if core utilization is below a threshold, frequency of the core can be reduced for performing polling of I/O events. If core utilization is at or above the threshold, frequency of the core can be increased used to performing polling of I/O events.