Adaptive Current Reversal Comparator for Synchronous Regulators

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Solution Overview

Problem

Current synchronous switching regulators face inefficiencies due to comparator propagation delays, which result in premature or delayed turning OFF of the synchronous transistor, leading to reduced efficiency as the comparator's offset calculation is not adaptable to varying output voltages and inductor values.

Innovation Solution

An adaptive current reversal comparator that automatically adjusts its offset voltage based on the time differential between the trip point and the end of the switching cycle, ensuring the synchronous transistor turns OFF at the point of current reversal, using a circuit that includes a resistor, capacitor, and logic gates to servo the offset voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a fixed offset voltage is used in the comparator, then the circuit design is simple, but the comparator trips too early or too late for varying output voltages and inductor values, resulting in lowered efficiency

Engineering Contradiction:
Improvecomparator circuit designVSAvoidregulator efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements dynamic offset adjustment by replacing the fixed offset voltage with a variable offset voltage that automatically adapts to different operating conditions. The offset voltage is generated by a voltage divider circuit (R1, R2, R3) that responds to changes in output voltage and inductor current, enabling the comparator to maintain optimal trip timing across varying load conditions without manual recalibration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms where the comparator monitors the actual current reversal timing and adjusts the offset voltage accordingly. The circuit uses the output voltage and inductor current information to continuously refine the offset value, creating a closed-loop system that optimizes efficiency by ensuring the synchronous transistor turns off precisely at current reversal regardless of operating conditions.

Inventive Principle:
Principle #23Feedback

2Ease of manufacture

If the comparator offset is manually calculated for specific output voltage and inductor value, then the design process is straightforward, but the comparator cannot adapt to different applications, leading to premature or delayed tripping

Engineering Contradiction:
Improvedesign processVSAvoidcomparator adaptability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal comparator circuit that can operate across multiple applications and operating conditions. The voltage divider network (R1, R2, R3) and associated circuitry enable the same comparator design to automatically adapt to different output voltages and inductor values without requiring redesign or manual offset calculation, making the regulator suitable for various applications from 3.3V to 12V outputs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20070247130A1Adaptive current reversal comparator
Publication Date: 2007.10.25 ANALOG DEVICES INT UNLTD CO
  • US20070247130A1 patent drawing
  • US20070247130A1 patent drawing
  • US20070247130A1 patent drawing

AI summary

An adaptive current reversal comparator for synchronous switching regulator comparison circuit for use in a switching regulator is provided. The comparison circuit includes a voltage offset that is used at least in part to compensate for a propagation delay of the comparison circuit. The switching regulator includes an inductor and a synchronous transistor. The comparison circuit also includes a timing circuit that provides a threshold amount of time and an offset adjustment circuit. The offset adjustment circuit preferably decreases the voltage offset of the comparison circuit when a synchronous transistor control signal transitions to an OFF state more than the threshold amount of time prior to the discharge of an inductor. The comparison circuit also increases the voltage offset of the comparison circuit when the synchronous control signal transitions to an OFF state more than the threshold amount of time following the discharge of the inductor.