Adaptive CVDD Voltage Tracking for SRAM Power Efficiency
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Solution Overview
Problem
Conventional SRAM arrays face limitations in reducing the minimum VDD supply voltage (VDD_min) due to fixed CVDD voltage requirements, which restricts power efficiency and scalability, especially in battery-powered devices, as the voltage offset between CVDD and VDD must be maintained within a narrow range to prevent erroneous operations.
Innovation Solution
An adaptive CVDD supply circuit using a bandgap reference generator and voltage follower to track the VDD voltage with an offset, allowing CVDD to adjust until reaching a maximum voltage, thereby enabling lower VDD_min levels while maintaining sufficient static noise margin (SNM) for SRAM arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CVDD voltage is fixed to maintain sufficient static noise margin (SNM), then SRAM array reliability is improved, but VDD_min cannot be reduced further limiting power efficiency
Solution Approach 1:
The patent implements a dynamic CVDD voltage adjustment mechanism where the CVDD voltage is no longer fixed but adapts to the operating conditions. The circuit automatically adjusts CVDD based on the voltage difference between CVDD and VDD, allowing VDD to be reduced while maintaining sufficient SNM through dynamic voltage tracking rather than static fixed voltage.
Solution Approach 2:
The patent employs a feedback mechanism using a voltage difference detection circuit that continuously monitors the voltage difference between CVDD and VDD. This feedback controls the CVDD adjustment circuit to maintain the voltage difference within an optimal range, ensuring reliable SRAM operation while enabling lower VDD_min for reduced power consumption.
2Use of energy by moving object
If CVDD voltage is reduced to enable lower VDD_min, then power efficiency is improved, but the voltage offset between CVDD and VDD becomes too large causing erroneous operation
Solution Approach 1:
The feedback mechanism continuously monitors the voltage difference between CVDD and VDD, and the CVDD adjustment circuit responds by modifying CVDD to maintain the offset within the safe range of 0.35-0.5V, preventing erroneous operation while maximizing power efficiency.
Solution Approach 2:
The patent changes the CVDD voltage parameter dynamically rather than keeping it fixed. The CVDD adjustment circuit modifies the CVDD voltage level based on operating conditions, allowing the system to achieve lower VDD_min for improved power efficiency while maintaining the necessary voltage offset for reliable operation.
3Device complexity
If fixed CVDD voltage is used in conventional SRAM designs, then design simplicity is maintained, but scalability to different processes and reduction in VDD_min are limited
Solution Approach 1:
The patent introduces dynamic voltage tracking capability that automatically adapts to different process technologies. The CVDD adjustment circuit responds to process variations and scaling requirements, enabling the SRAM design to be scaled to different process nodes (90nm, 65nm, 45nm, 32nm, 28nm) without redesign while maintaining proper voltage relationships.
Solution Approach 2:
The patent creates a universal SRAM design that can operate across multiple process technologies and voltage conditions. The adaptive CVDD mechanism provides multi-functionality by automatically adjusting to different process characteristics and scaling requirements, making the design reusable and scalable without sacrificing simplicity.
Data Source
AI summary
Circuit and methods for providing the CVDD supply to the cells in an SRAM array while maintaining a desired VDD voltage. A circuit is described for tracking the VDD supply voltage and providing a CVDD supply for the SRAM cells that maintains an offset above VDD until a maximum voltage for the CVDD voltage is reached. The CVDD voltage supplies the word line drivers and the cells in an SRAM array, while the bit line precharge and the remaining circuitry is operated on the VDD supply. By maintaining a maximum offset between the voltage CVDD and the supply voltage VDD, the SRAM will have the required static noise margins for reliable operation, while a lowered VDD_min voltage may also be obtained. A method for supplying a CVDD voltage to an SRAM cell array is disclosed where the CVDD voltage tracks a VDD supply voltage plus a predetermined offset voltage.