Adaptive DAC Error Cancellation for Amplitude and Timing Correction
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Solution Overview
Problem
Existing digital to analog converters (DACs) face challenges in accurately correcting amplitude and timing errors, which adversely affect Spurious-Free Dynamic Range (SFDR) performance, often requiring high over-sampling ratios and complex digital logic.
Innovation Solution
The system employs an integrator to capture the energy of the DAC output, using an analog to digital converter (ADC) to digitize this voltage, and a summer to form an error signal that is fed into an adaptation circuit to adjust DAC cells for amplitude and timing corrections, eliminating the need for high-complexity digital logic and allowing sub-sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high over-sampling ratios and complex digital logic are used to correct amplitude and timing errors, then DAC accuracy is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent replaces complex digital logic systems with an analog-based error detection and correction mechanism. An integrator circuit accumulates timing and amplitude errors in the analog domain, and a DAC generates correction signals based on this integrated error, eliminating the need for complex digital processing while maintaining correction accuracy
Solution Approach 2:
The integrator serves as an intermediary component that bridges the DAC output and the correction mechanism. It accumulates errors over time and converts them into a form that can be used to generate correction signals, simplifying the overall error correction architecture
2Measurement precision
If high over-sampling ratios are used to capture timing errors accurately, then timing error measurement precision is improved, but sampling rate and power consumption increase
Solution Approach 1:
The integrator performs preliminary accumulation of timing errors over multiple cycles before generating correction signals. This allows accurate timing error measurement to be achieved without requiring high instantaneous sampling rates, as the error integration process naturally averages out timing variations
Solution Approach 2:
The error correction system operates periodically, with the integrator accumulating errors over time and generating correction signals at appropriate intervals. This periodic operation allows accurate timing error capture without continuous high-rate sampling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances DAC accuracy by accurately correcting both amplitude and timing errors without over-sampling, enabling faster operation and reduced power consumption while maintaining high SFDR performance.
Implementation Method 1
an integrator to integrate an output of the digital to analog converter
Data Source
Figure 1~2
Figure 3A
Figure 3B~3C
AI summary
The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion circuit can includes a digital input, an analog output, and a cell array. The digital to analog converter can also include an integrator, an analog to digital converter (ADC), and a summer coupled to the ADC, and an adaptation circuit coupled to the summer. The adaption circuit provides controls signals to the cell array.