Adaptive Resistor Network in DAC Cells for Low Noise and Mismatch
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Solution Overview
Problem
Traditional digital-to-analog converters (DACs) face challenges in maintaining maximum degeneration voltage at nominal full-scale currents, leading to increased output noise and mismatch.
Innovation Solution
The implementation of a digital-to-analog converter with an adjustable resistor network, where the resistance is adapted based on the bias current to maximize degeneration voltage, reducing noise and mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional DACs operate at nominal full-scale currents, then the circuit is simpler and more compact, but the degeneration voltage decreases leading to increased output noise and mismatch
Solution Approach 1:
The patent applies the dynamics principle by making the resistor network adjustable rather than fixed. The resistor network can dynamically change its resistance value based on the operating conditions (full-scale current level) to maintain optimal degeneration voltage. This allows the DAC to adapt to different current levels and maintain low noise and mismatch performance across varying operating points without requiring a completely different circuit design.
Solution Approach 2:
The patent implements parameter changes by varying the resistance value of the resistor network according to the bias current level. When the full-scale current is reduced to nominal levels, the resistor network adjusts its resistance to compensate and maintain the degeneration voltage at optimal levels. This parameter adjustment resolves the contradiction by allowing the same compact circuit to perform well at both high and low current levels.
2Object-affected harmful factors
If the degeneration voltage is maximized to reduce output noise and mismatch, then the performance improves, but the circuit complexity increases
Solution Approach 1:
The patent applies universality by designing a resistor network that serves multiple functions: it provides the necessary degeneration resistance for low noise and mismatch performance, while also being adjustable to adapt to different full-scale current levels. This multi-functional design eliminates the need for separate circuits optimized for different operating conditions, thereby maintaining relatively simple overall circuit complexity while achieving high performance across various scenarios.
Solution Approach 2:
The resistor network is configured to automatically adjust its resistance based on the bias current level without requiring external control circuitry. The adjustment mechanism is integrated into the resistor network itself, allowing it to self-regulate and maintain optimal degeneration voltage based on the operating conditions. This self-service capability reduces the need for additional complex control circuits.
Data Source
AI summary
Methods and apparatus for adaptively adjusting a resistance of a resistor network in a digital-to-analog converter (DAC), such as a current-steering DAC for a transmit chain. An example DAC generally includes a plurality of DAC cells. One or more of the DAC cells generally includes a current source and a resistor network. The resistor network includes a plurality of resistive elements, has an adjustable resistance, and is coupled between a power supply rail and the current source. In this manner, the DAC may support a wide range of full-scale currents, while maintaining a higher degeneration voltage and reduced noise and mismatch for a given headroom. For certain aspects, the one or more of the DAC cells further include a plurality of switches (e.g., implemented with PFETs) coupled to one or more of the resistive elements and configured to adjust the resistance of the resistor network.