Adaptive Data Transmission Order for Multi-Plane Memory Read Bottlenecks

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Solution Overview

Problem

The standardized data reading mechanism in rewritable non-volatile memory modules leads to inefficiencies in system performance when handling read commands for different planes in the same chip enable region, resulting in wasted performance.

Innovation Solution

A data reading method that determines a customized data transmission order based on the performance of read operations across planes within a chip enable region, ensuring that data is transmitted sequentially according to the efficiency of each operation, thereby optimizing the reading performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If read commands for different planes are executed in sequential receiving order, then the standardized reading mechanism is maintained, but system performance is wasted due to inefficient data transmission ordering

Engineering Contradiction:
Improvedata reading performanceVSAvoidreading mechanism complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the data transmission order adaptive rather than fixed. The memory control circuit unit dynamically determines the transmission order based on real-time read operation performance of different planes, allowing the system to optimize data transmission efficiency under varying operational conditions while maintaining a standardized reading mechanism framework.

Inventive Principle:
Principle #15Dynamics

2Productivity

If data is transmitted in standardized sequential order from multiple planes, then the reading mechanism remains simple, but bandwidth utilization is suboptimal due to ignoring varying read operation performance

Engineering Contradiction:
Improvebandwidth utilizationVSAvoiddata transmission time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent changes the transmission order parameter based on read operation performance metrics. Instead of using a fixed sequential transmission order, the system adjusts the transmission sequence by evaluating performance parameters of read operations across different planes, thereby optimizing bandwidth utilization and reducing data transmission time.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If the memory control circuit unit monitors and compares read operation performance across planes, then optimized data transmission order is achieved, but the control mechanism becomes more complex

Engineering Contradiction:
Improvesystem efficiencyVSAvoidcontrol mechanism complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements feedback by having the memory control circuit unit monitor read operation performance of different planes and use this information to determine the optimal data transmission order. The performance metrics from read operations feed back into the control logic, enabling the system to adaptively optimize transmission sequencing without requiring overly complex external control mechanisms.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12093532B2Data reading method, memory storage device, and memory control circuit unit
Publication Date: 2024.09.17 PHISON ELECTRONICS
  • US12093532B2 patent drawing
  • US12093532B2 patent drawing
  • US12093532B2 patent drawing

AI summary

A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving multiple read commands at least instructing to read first data stored in a first plane and second data stored in a second plane from a host system; sending multiple read command sequences at least instructing to execute a first read operation on the first plane to obtain the first data and to execute a second read operation on the second plane to obtain the second data according to the read commands; determining a data transmission order according to performance of the first read operation and the second read operation; and sequentially receiving the first data and the second data from a rewritable non-volatile memory module according to the data transmission order.