Adaptive Dead Time Control in Voltage Regulator Switching Circuits

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Solution Overview

Problem

Existing voltage regulator circuits face challenges in effectively controlling the duration of dead time between high side and low side switches, which affects output voltage stability and efficiency.

Innovation Solution

A circuit with a variable delay control mechanism that adjusts high side and low side delay times based on timing differences between control signals, allowing for programmable adaptive dead times to optimize switching operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a fixed dead time is used between high side and low side switches, then the circuit structure is simple, but power efficiency deteriorates and body diode conduction occurs

Engineering Contradiction:
Improvecircuit structureVSAvoidpower efficiency
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent implements a variable dead time mechanism where the dead time period dynamically adjusts based on switching conditions. The controller modifies the dead time duration according to detected timing differences between complementary switching signals, enabling the system to adapt to varying load conditions and manufacturing variations, thereby eliminating body diode conduction and improving power efficiency without excessive complexity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs a feedback mechanism where the controller detects the timing difference between the falling edge of the first complementary switching signal and the rising edge of the second complementary switching signal. Based on this detected timing difference, the controller adjusts the dead time period to ensure proper switching sequencing, preventing body diode conduction and optimizing power efficiency through closed-loop control

Inventive Principle:
Principle #23Feedback

2Reliability

If dead time is extended to prevent body diode conduction, then reliability improves, but productivity deteriorates due to increased loss of time

Engineering Contradiction:
Improveswitching controlVSAvoidswitching frequency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements a variable dead time mechanism where the dead time period dynamically adjusts based on switching conditions. The controller modifies the dead time duration according to detected timing differences between complementary switching signals, enabling the system to adapt to varying load conditions and manufacturing variations, thereby eliminating body diode conduction and improving power efficiency without excessive complexity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the dead time parameter dynamically based on detected timing differences. By adjusting the dead time duration as a variable parameter rather than using a fixed value, the system achieves reliable switching control while minimizing the time loss, thus maintaining high switching frequency and productivity

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240429811A1Voltage regulator having programmable adaptive dead time
Publication Date: 2024.12.26 EMPOWER SEMICONDUCTOR INC
  • US20240429811A1 patent drawing
  • US20240429811A1 patent drawing
  • US20240429811A1 patent drawing

AI summary

An electronic circuit is disclosed. The electronic circuit includes a switching circuit that includes a high side switch connected to a low side switch at a switch node, a controller arranged to generate a high side control signal and a low side control signal, a variable delay circuit arranged to receive the high side control signal and in response transmit a corresponding delayed high side control signal, and to receive the low side control signal and in response transmit a corresponding delayed low side control signal, a high side driver circuit arranged to transmit a high side drive signal to the high side switch in response to receiving the delayed high side control signal, and a low side driver circuit arranged to transmit a low side drive signal to the low side switch in response to receiving the delayed low side control signal.