Adaptive Decimation Control in ASRCs to Prevent Signal Folding

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Solution Overview

Problem

Existing asynchronous sample rate converters face challenges in preventing signal folding from the passband of the input sample rate into the output sample rate without increasing the order of the low pass filter or the interpolation ratio, leading to inefficiencies in area and power consumption.

Innovation Solution

Adaptive decimation rate control in asynchronous sample rate converters, utilizing a digital phase-locked loop to determine the input to output sampling rate ratio, allowing for dynamic adjustment of the decimation rate and bypassing stages to maintain low pass filter performance while reducing power and area requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the order of the low pass filter is increased to prevent signal folding, then signal folding is prevented, but chip area and power consumption increase significantly

Engineering Contradiction:
Improvesignal folding preventionVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent implements dynamic adjustment of the decimation ratio based on the relationship between input sampling rate (Fsin) and output sampling rate (Fsout). When Fsin > Fsout, the system automatically increases the decimation ratio to prevent signal folding, and when Fsin ≤ Fsout, it reduces the decimation ratio to minimize resource usage. This dynamic control mechanism allows the system to adapt to different operating conditions without requiring a permanently high-order low pass filter, thereby preventing signal folding while optimizing chip area and power consumption.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the decimation ratio is increased to prevent signal folding, then signal folding is prevented, but power consumption and chip area increase

Engineering Contradiction:
Improvesignal folding preventionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The system dynamically adjusts the decimation ratio based on the ratio of input to output sampling rates. When signal folding risk is detected (Fsin > Fsout), the decimation ratio is increased to prevent folding. When folding risk is absent (Fsin ≤ Fsout), the decimation ratio is reduced to minimize power consumption. This conditional dynamic adjustment ensures signal folding prevention only when necessary, optimizing power efficiency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the decimation ratio parameter dynamically based on operating conditions. By monitoring the relationship between Fsin and Fsout, the system adjusts the decimation ratio to appropriate levels, ensuring sufficient attenuation of folded signals only when needed. This parameter adaptation allows the system to maintain signal integrity while minimizing power consumption during normal operation.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If a fixed temporary sampling rate is used with external decimation, then signal folding is prevented, but the system requires additional external components and increases complexity

Engineering Contradiction:
Improvesignal folding preventionVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the decimation functionality directly into the ASRC chip by integrating the decimation filter and control logic. Instead of requiring an external decimation filter as a separate component, the system combines interpolation, filtering, and decimation operations within a single integrated device. This integration eliminates the need for external components while maintaining signal folding prevention capabilities, thereby reducing system complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The ASRC system is designed to perform multiple functions within a single device: interpolation, low pass filtering, adaptive decimation, and signal folding prevention. By making the system universal and self-sufficient, it eliminates the need for external decimation filters and reduces overall system complexity while maintaining all necessary signal processing capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8849883B2Method and apparatus for adaptive control of the decimation ratio in asynchronous sample rate converters
Publication Date: 2014.09.30 ANALOG DEVICES INC
  • US8849883B2 patent drawing
  • US8849883B2 patent drawing
  • US8849883B2 patent drawing

AI summary

An asynchronous sample rate converter prevents the folding back of a signal in the passband of an input sample rate into the passband of the output sample by adaptively controlling the decimation rate. The ASRC includes an adaptive decimation rate controller that selectably controls a decimation filter based on the ratio of the input sampling rate to the output sampling rate. By adaptively controlling the decimation rate in the ASRC, a significant amount of area and power is saved.