Adaptive Iterative Decoder Node Control for Lower Power LDPC Decoding
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Solution Overview
Problem
Iterative decoding in forward error correction (FEC) circuits, such as LDPC decoding, consumes high power due to increased decoding frequency and complexity, leading to significant power dissipation, often exceeding 50% of the chip's total power consumption.
Innovation Solution
An iterative decoder architecture that dynamically controls the number of enabled nodes based on criteria like false parity sums, signal-to-noise ratio, and decoding convergence, allowing for flexible power reduction without compromising performance by using subsets of variable and check node processors, and optimizing memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative decoding is used to improve error correction performance, then decoding performance is improved, but power consumption increases significantly
Solution Approach 1:
The patent applies dynamics by making the decoder configuration adaptive and changeable during operation. The system dynamically adjusts the number of enabled check node processors and variable node processors based on decoding progress and performance metrics, allowing the power consumption to be optimized in real-time while maintaining error correction performance.
Solution Approach 2:
The patent segments the decoder into multiple independent check node processors and variable node processors that can be individually enabled or disabled. This segmentation allows selective activation of processing units based on the decoding state, reducing overall power consumption while maintaining necessary error correction functionality.
2Productivity
If the number of processing nodes is increased to improve decoding throughput, then productivity is improved, but device complexity and power consumption increase
Solution Approach 1:
The system dynamically adjusts the number of active processing nodes based on throughput requirements and decoding state. The controller monitors decoding progress and adaptively enables or disables processing units, allowing the decoder to scale its complexity and throughput dynamically rather than being fixed at maximum capacity.
Solution Approach 2:
The patent designs processing nodes with multi-functionality where check node processors and variable node processors can be selectively activated. The same hardware infrastructure supports both high-throughput operation (when all nodes are active) and low-power operation (when fewer nodes are active), providing universal functionality across different operating conditions.
3Speed
If full parallel processing is used to reduce decoding time, then speed is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by alternating between phases of intensive parallel processing and phases of reduced processing activity. The controller periodically evaluates decoding convergence and adjusts the number of active processing units accordingly, creating a rhythm of high-speed processing followed by power-saving states.
Solution Approach 2:
The system applies partial action by activating only the necessary number of processing nodes required to achieve the desired decoding speed, rather than always using full parallel processing. This allows the decoder to operate at maximum speed when needed while consuming less power during normal operation.
Data Source
AI summary
A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include performing iterative decoding on a demodulated signal to provide a decoded signal, receiving information regarding the iterative decoding, and based on the information controlling a number of nodes of the iterative decoder to enable during a next iteration of the iterative decoding.