Memory Control Circuit for Adaptive Decoding Under Cell Interference

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Solution Overview

Problem

The increasing interference between memory cells in rewritable non-volatile memory modules leads to higher bit error rates, making it difficult for decoding circuits to accurately decode data, especially when inappropriate decoding parameters are used, and cross-physical unit decoding may fail due to insufficiently decoded data within the same encoding group.

Innovation Solution

A decoding parameter updating method that involves sending reading command sequences to read data from multiple physical units at different voltage levels, performing logical operations to obtain decoding index information, and updating decoding parameters based on error evaluation information to improve decoding success rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the data storage density of the rewritable non-volatile memory module is increased, then the storage capacity is improved, but the interference between memory cells increases resulting in higher bit error rates

Engineering Contradiction:
Improvedata storage densityVSAvoidbit error rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting decoding parameters (such as threshold values and voltage levels) based on the actual read results and error evaluation information. The memory control circuit unit modifies decoding parameters according to the voltage intervals and error rates observed during reading operations, allowing the system to adapt to varying interference conditions while maintaining high storage density

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If the decoding parameter is fixed and inappropriate, then the decoding circuit operates simply, but the decoding success rate decreases

Engineering Contradiction:
Improvedecoding parameter adjustment mechanismVSAvoiddecoding success rate
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements dynamics by transitioning from fixed decoding parameters to dynamic, adaptive parameters. The memory control circuit unit continuously monitors read results and error evaluation information, then adjusts decoding parameters in real-time based on the actual decoding conditions. This dynamic adjustment mechanism ensures optimal decoding performance across varying storage densities and interference levels

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs feedback by using error evaluation information derived from read results to modify decoding parameters. The memory control circuit unit receives feedback about decoding success rates and error rates, then uses this information to optimize future decoding operations. This closed-loop feedback system ensures that decoding parameters are continuously improved based on actual performance

Inventive Principle:
Principle #23Feedback

3Reliability

If cross-physical unit decoding is performed, then the decoding capability is improved, but the decoding complexity increases

Engineering Contradiction:
Improvecross-physical unit decoding capabilityVSAvoiddecoding process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the decoding process into manageable segments based on voltage intervals and physical units. The memory control circuit unit processes data from different physical units separately, organizing them by voltage intervals and handling each segment with appropriate decoding parameters. This segmented approach enables cross-physical unit decoding while maintaining manageable complexity through systematic organization

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12443521B2Decoding parameter updating method, memory storage device and memory control circuit unit
Publication Date: 2025.10.14 PHISON ELECTRONICS
  • US12443521B2 patent drawing
  • US12443521B2 patent drawing
  • US12443521B2 patent drawing

AI summary

A decoding parameter updating method, a memory storage device, and a memory control circuit unit are disclosed. The method includes the following. A reading command sequence is sent to a rewritable non-volatile memory module to instruct reading of first data from a first physical unit based on multiple read voltage levels. A logical operation is performed on a first data group to obtain decoding index information corresponding to the first data group. The first data group includes the first data and second data read from a second physical unit. Error evaluation information corresponding to a first voltage interval among multiple voltage intervals is obtained according to the first data and the decoding index information. A first decoding parameter corresponding to the first voltage interval is updated according to the error evaluation information.