Adaptive Delay Monitoring for Critical Path Timing Margins
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Computing systems are vulnerable to attacks through side channel attacks and physical fault injection, which can disrupt their operation by manipulating environmental factors like voltage, temperature, or electromagnetic radiation, leading to timing violations and data corruption.
Innovation Solution
Implementing a delay monitoring scheme that adapts operational parameters such as supply voltage, back-gate bias, or frequency by using adaptive monitoring circuits with delay elements and comparison elements to maintain critical path timing margins, thereby detecting and mitigating timing violations caused by environmental changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sign-off with worst-case corner simulations is used to guarantee timing margins, then reliability is improved, but device complexity increases due to extensive simulation requirements
Solution Approach 1:
The system uses self-service by implementing on-chip delay monitoring circuits that automatically measure timing margins during actual operation. The monitoring circuitry embedded within the processor continuously tracks critical path delays and provides real-time feedback, eliminating the need for extensive external simulations while maintaining reliability guarantees.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting operational parameters such as voltage and frequency based on measured timing margins. The system modifies these parameters in real-time to maintain optimal timing margins, replacing static worst-case design assumptions with adaptive parameter adjustment based on actual measured conditions.
2Reliability
If fixed design margins are used to ensure correct operation under all conditions, then reliability is improved, but productivity decreases due to lower operating frequency
Solution Approach 1:
The system implements dynamics by transitioning from fixed design margins to dynamic timing margin adjustment. The monitoring circuit continuously measures actual timing margins and enables the system to adaptively adjust operating frequency and voltage in real-time, allowing the processor to operate at higher frequencies when conditions permit while maintaining reliability.
Solution Approach 2:
The patent applies parameter changes by dynamically modifying operational parameters including frequency and voltage based on measured timing margins. This replaces static fixed-margin design with adaptive parameter adjustment, enabling higher productivity when timing margins allow while maintaining correct operation when margins are tight.
3Productivity
If higher operating frequency is implemented to improve productivity, then productivity is improved, but reliability worsens due to reduced timing margins
Solution Approach 1:
The system implements feedback by using on-chip delay monitoring circuits that continuously measure critical path timing margins and provide real-time feedback to the control logic. This feedback mechanism enables dynamic adjustment of operating frequency and voltage to maintain reliability while maximizing productivity, replacing open-loop fixed-frequency operation with closed-loop adaptive control.
Solution Approach 2:
The patent applies dynamics by enabling the system to dynamically adjust operating frequency and voltage based on real-time timing margin measurements. This dynamic adaptation allows the system to operate at higher frequencies when timing margins are sufficient while automatically reducing frequency when margins become tight, optimizing the trade-off between productivity and reliability.
4Reliability
If extensive timing margins are maintained to ensure correct operation, then reliability is improved, but use of energy increases due to higher voltage requirements
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting voltage and frequency based on measured timing margins. The system reduces voltage and frequency when timing margins are sufficient, thereby reducing power consumption while maintaining correct operation. This replaces static high-voltage operation with adaptive parameter adjustment that minimizes energy usage.
Solution Approach 2:
The system implements dynamics by transitioning from static voltage/frequency operation to dynamic adjustment based on real-time timing margin measurements. The monitoring circuit enables the system to adaptively scale voltage and frequency, reducing power consumption when full performance is not needed while maintaining reliability when timing margins require higher operating parameters.
Data Source
AI summary
A monitoring system for monitoring delay of critical path timing margins can include a plurality of adaptive monitoring circuits, where each adaptive monitoring circuit is coupled to a corresponding one of a plurality of paths in a circuit. Each adaptive monitoring circuit can include a first delay element designed to cause a mean timing margin of the plurality of N paths in the circuit to be within one minimum mean unit delay; a second delay element coupled to the first delay element and designed to add a mean delay of k*σmax; a set-up capture element capturing an output of the second delay element; and a set-up warning comparison element that outputs a set-up warning signal when the output of the set-up capture element and a shadow capture element or a capture element of the corresponding one of the plurality of paths do not satisfy an expected condition.