Adaptive Cyclic Delay Line for Fractional-N PLL Phase Stability
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Solution Overview
Problem
Existing phase-locked loops (PLLs) face challenges in maintaining stable phase lock and minimizing jitter and noise spurs, particularly when operating in fractional-N division mode.
Innovation Solution
The implementation of a PLL circuit that includes a delay circuit and an adaptive gain circuit. The delay circuit provides progressively larger delays to the divided output clock within each division cycle, and the adaptive gain circuit adjusts the gain based on phase error samples to optimize the delay and maintain phase lock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fractional-N divider is used to achieve higher frequency multiplication, then the output frequency range is improved, but phase noise and jitter increase
Solution Approach 1:
The feedback division is segmented into multiple integer division stages rather than using a single fractional division. The first divider performs integer division by N1, and the second divider performs integer division by N2, where the product N1×N2 equals the desired fractional multiplication factor. This segmentation eliminates the phase noise and jitter inherent in fractional-N division while achieving the same frequency multiplication through cascaded integer divisions.
2Adaptability or versatility
If the feedback division ratio is changed to achieve frequency tuning, then the frequency range is improved, but phase lock stability deteriorates
Solution Approach 1:
The system dynamically adjusts the division ratios N1 and N2 in the cascaded integer dividers based on the desired output frequency. By maintaining the constraint that N1×N2 equals the target fractional multiplication factor, the system achieves wide frequency tuning range while preserving phase lock stability through integer division mechanics, avoiding the instability associated with fractional division ratio changes.
3Device complexity
If a simple integer divider is used in the feedback path, then the circuit complexity is reduced, but the frequency multiplication accuracy deteriorates
Solution Approach 1:
Instead of using a single complex fractional-N divider, the system segments the frequency multiplication into two simpler integer division stages. Each divider operates with an integer ratio (N1 and N2 respectively), simplifying the circuit design while achieving the same overall multiplication accuracy through the product N1×N2. This segmented approach reduces individual divider complexity while maintaining overall frequency precision.
Data Source
AI summary
Embodiments herein relate to a phase-locked loop (PLL) circuit which compensates for varying delays in a feedback clock signal which are caused by the use of fractional division. In one aspect, a delay circuit is used to provide progressively larger delays for the feedback clock signal within each division cycle, when the divider uses the smaller divisor, N. This compensates for the associated larger frequency and smaller clock cycle, compared to when the divisor is N+1. Additionally, the delays introduced by the delay circuit can be controlled by an adaptive gain circuit. The adaptive gain circuit samples a phase error of a phase detector of the PLL to determine whether to increase or decreases the gain, thereby increasing or decreasing, respectively, the delay.