Adaptive Demodulator Sampling for Faster Binary Signal Detection
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Solution Overview
Problem
Conventional radio frequency signal demodulators face limitations in transmission speed due to signal disturbances and compatibility issues with clock frequencies, resulting in low data flow rates, making it impractical for applications like image transmission.
Innovation Solution
A demodulation circuit that uses an analog-to-digital conversion with a sampling signal of shorter period, selects a reduced number of significant samples, and applies a majority decision criterion to determine binary states, allowing for increased data flow rates while being compatible with existing architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional single-point sampling is used, then the system is simple to implement, but the data transmission speed is limited to 106 kilobits per second
Solution Approach 1:
The patent divides the symbol duration into multiple sampling points (at least two different instants within one symbol period). Instead of taking a single sample per symbol, the system segments the sampling process across multiple time points, allowing faster data rates while maintaining compatibility with the CPU clock frequency.
Solution Approach 2:
The patent performs preliminary sampling at multiple points within each symbol period before the final decision is made. This preliminary multi-point sampling allows the system to prepare data at a higher rate than the CPU can process, then selectively use subsets of these samples to match the CPU's processing capability.
2Productivity
If sampling frequency is increased to boost data rate, then transmission speed improves, but signal disturbances cause erroneous results
Solution Approach 1:
The patent implements a decision feedback mechanism where the binary state is determined by comparing multiple samples and selecting the one that provides the most reliable decision. The system uses feedback from multiple sampling points to overcome signal disturbances, ensuring that the final decision is based on the most accurate sample rather than being misled by transient disturbances.
Solution Approach 2:
The system performs preliminary sampling at multiple points within each symbol period, allowing it to anticipate and prepare for potential signal disturbances. By having multiple pre-sampled values available, the system can select the most reliable sample for the final decision, thereby maintaining high data rates while improving reliability.
3Productivity
If multiple samples per symbol are taken, then data rate increases, but compatibility with CPU clock frequency becomes problematic
Solution Approach 1:
The patent employs dynamic selection of sampling points and adaptive determination of binary states based on multiple samples. The system can dynamically adjust which samples are used for decision-making, allowing it to operate at higher data rates while remaining compatible with the fixed CPU clock frequency through flexible, adaptive processing.
Solution Approach 2:
The system segments the high-rate sampling process into multiple discrete points within each symbol period, then selectively processes these segments to match the CPU's processing capability. This segmentation allows the front-end to operate at high speed while the back-end remains compatible with existing CPU architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data transmission speed by up to 8 times, improving reliability and compatibility with existing systems, enabling faster image transmission and analysis in applications like authentication and access control.
Implementation Method 1
an analog-to-digital conversion element using a sampling signal based on a frequency having a period shorter than the duration of a symbol
Data Source
AI summary
A method and a circuit for detecting a binary state supported by an analog symbol, comprising sampling the symbol with a sampling signal based on a frequency having a period shorter than the duration of a symbol, selecting a number of significant samples smaller than the number of samples which would be obtained with a sampling of the symbol at said frequency, and deciding of the symbol state based on the selected samples.