Memory PHY Interface With Adaptive DFE Reset Timing
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Solution Overview
Problem
Existing memory apparatuses face challenges in effectively resetting the DFE tap between read bursts due to varying gaps between bursts across different frequencies, making it difficult to meet timing requirements.
Innovation Solution
A memory apparatus with a DFE reset circuit that generates a DFE reset signal based on both a gate enable signal and an internal enable signal, allowing the DFE tap to be reset between read bursts, and includes an AND gate to route the DFE reset signal with similar delay as the data strobe signal to meet timing, thereby automatically tracking voltage-temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed reset timing is used for DFE tap, then the reset can be implemented simply, but it cannot meet timing requirements across different frequencies due to varying gaps between read bursts
Solution Approach 1:
The patent applies dynamics by making the reset timing adaptive rather than fixed. The DFE reset circuit dynamically adjusts the reset timing based on the actual gap between read bursts, which varies with frequency. This is achieved by using a delay circuit that can be configured to provide different delay times, allowing the reset signal to be generated at the appropriate moment regardless of the operating frequency or burst gap duration.
Solution Approach 2:
The patent changes the timing parameter of the reset signal based on operating conditions. By modifying the delay time parameter in the delay circuit, the system can accommodate different frequencies and burst gaps. This parameter adjustment allows the same reset circuit to function correctly across a range of frequencies without requiring complex frequency-dependent design.
2Reliability
If the DFE tap is reset using a simple reset signal, then the circuit is simpler, but it cannot automatically track voltage-temperature variations
Solution Approach 1:
The patent incorporates feedback by using the data strobe signal, which reflects the actual data transmission timing and is affected by voltage-temperature variations, to control the reset timing. The delay circuit is configured based on the data strobe signal timing, creating a feedback loop that automatically adapts to VT variations. This ensures the reset occurs at the correct moment even under varying operating conditions.
Solution Approach 2:
The reset circuit performs self-service by automatically adjusting its timing based on the data strobe signal without external intervention. The system uses the data strobe signal itself to determine when to generate the reset signal, allowing the circuit to self-regulate and track voltage-temperature variations independently.
3Manufacturing precision
If the reset timing is adjusted for each frequency, then timing accuracy is improved, but the circuit complexity increases significantly
Solution Approach 1:
The patent achieves universality by designing a single reset circuit that can handle multiple frequencies and burst gap durations. The delay circuit is configured to provide appropriate delay for different operating conditions, allowing one circuit design to serve multiple frequency requirements. This eliminates the need for separate reset circuits for each frequency, maintaining timing precision while reducing overall complexity.
Data Source
AI summary
A memory apparatus includes a DFE receiver and a DFE reset circuit. The DFE receiver is configured to receive a data signal and a data strobe signal from a memory device. The DFE receiver includes a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap. The DFE reset circuit is configured to receive a gate enable signal and an internal enable signal from the memory controller, generate a DFE reset signal according to the gate enable signal and the internal enable signal. The DFE reset circuit outputs the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.