Adaptive DFE Clock Timing in Receiver Equalizer Circuits
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Solution Overview
Problem
In high-frequency wired communication systems, channel losses due to skin and dielectric effects lead to significant signal intensity loss, particularly at Nyquist frequencies, causing inter-symbol interference and deteriorating data recovery accuracy.
Innovation Solution
A semiconductor integrated circuit with an equalizer circuit comprising a CTLE and DFE, where the DFE adjusts feedback timing based on sampling results to compensate for signal attenuation and inter-symbol interference, utilizing a summer circuit, correction circuit, variable delay circuit, and adjustment circuit to synchronize clock phases and improve signal recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-frequency wired communication is performed, then communication speed is improved, but signal intensity loss increases due to skin and dielectric effects
Solution Approach 1:
The patent implements a feedback mechanism where the reception device measures signal quality metrics (such as BER or SNR) and sends feedback information to the transmission device. Based on this feedback, the transmission device dynamically adjusts transmission parameters including modulation scheme, coding rate, and power allocation to compensate for signal attenuation caused by skin and dielectric effects at high frequencies.
Solution Approach 2:
The patent employs adaptive parameter adjustment where communication parameters (modulation order, coding rate, subcarrier spacing) are dynamically changed based on channel conditions. When signal intensity loss increases at high frequencies, the system transitions to more robust parameters (lower modulation order, higher coding rate) to maintain reliable communication.
2Productivity
If high-frequency communication is performed, then data transmission rate is improved, but inter-symbol interference increases causing deterioration of data recovery accuracy
Solution Approach 1:
The patent applies equalization techniques as a preliminary action to compensate for anticipated inter-symbol interference before data recovery. The equalizer pre-processes the received signal by applying inverse filtering based on the channel impulse response, thereby correcting distortion and eliminating ISI effects before the data is sampled and decoded.
Solution Approach 2:
The patent introduces an intermediary equalization stage between the received signal and the data recovery process. This intermediary component (equalizer) acts as a mediator that processes the distorted signal, removing inter-symbol interference and preparing a cleaned signal for accurate data recovery, thus decoupling the high data rate transmission from the accuracy requirement.
3Device complexity
If fixed feedback timing is used in DFE circuit, then circuit complexity is reduced, but data recovery accuracy deteriorates due to timing mismatch
Solution Approach 1:
The patent implements dynamic feedback timing adjustment in the DFE circuit where the feedback tap timing is no longer fixed but adapts to channel conditions. The system dynamically determines optimal feedback timing based on channel impulse response measurements or signal quality metrics, allowing the feedback samples to be taken at the most appropriate moments for maximum equalization effectiveness.
Solution Approach 2:
The DFE circuit performs self-adjustment of feedback timing by monitoring the quality of equalized output and automatically adjusting the timing of feedback samples. The circuit uses built-in timing detection mechanisms to identify optimal feedback sampling points without requiring external control, thereby maintaining high data recovery accuracy while avoiding complex external timing control circuits.
Data Source
AI summary
According to one embodiment, in a semiconductor integrated circuit, a variable delay circuit is electrically connected to the correction circuit and configured to change a delay amount of the second clock. An adjustment circuit is electrically connected to a summer circuit. The adjustment circuit is configured to perform sampling of values in a plurality of edge periods and values in a plurality of data periods of data output from the summer circuit, and adjust a delay amount of the variable delay circuit such that timing of the second clock supplied from the variable delay circuit to the correction circuit becomes close to target timing according to a plurality of sampling results.