Adaptive Non-Speculative DFE for PAM-4 Receivers
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Solution Overview
Problem
Current Decision Feedback Equalizers (DFEs) for PAM-4 signaling face stringent timing constraints, particularly in high-data-rate applications, leading to inefficient ISI cancellation and increased hardware requirements due to the need for speculative DFEs, which consume more resources and are less efficient.
Innovation Solution
An adaptive non-speculative DFE with an extended time constraint is proposed, incorporating a Continuous-Time Linear Equalizer (CTLE), Track and Hold (T&H) circuit, and a sampler with separate DFE and DATA sampling clock phases, allowing for increased settling time and reduced hardware through the use of Low Voltage Differential Signaling (LVDS) taps and the SS-LMS algorithm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a direct DFE is used to remove ISI in the next sample based on preceding samples, then the number of samplers is minimized, but the timing constraints become extremely stringent and may not be met at high data rates
Solution Approach 1:
The patent segments the sampling process into two distinct phases: a DFE sampling clock phase for equalization and a DATA sampling clock phase for data extraction. This segmentation allows the DFE to operate with relaxed timing constraints while maintaining efficient ISI cancellation, resolving the contradiction between minimizing samplers and satisfying timing constraints.
Solution Approach 2:
The patent performs preliminary equalization action by sampling the equalized signal in the DFE sampling clock phase before the actual data extraction in the DATA sampling clock phase. This preliminary action allows the DFE to prepare the signal for optimal sampling without being constrained by the tight timing requirements of high-speed data extraction.
2Reliability
If a speculative DFE is used to select the most reliable data among all cases, then timing constraints are relaxed, but an excessive number of samplers and multiplexers are used, particularly for PAM4 signaling
Solution Approach 1:
The patent extracts the essential function of speculative DFE (reliable data selection) while eliminating the excessive hardware components (multiplexers and additional samplers). By using a single sampler with dual clock phases, the patent achieves the same reliability benefit without the hardware overhead, resolving the contradiction between timing constraint satisfaction and device complexity.
Solution Approach 2:
The patent makes the single sampler multi-functional by using it for both DFE sampling (equalization) and DATA sampling (data extraction) through different clock phases. This universal approach eliminates the need for separate samplers and multiplexers required in speculative DFE, achieving both relaxed timing constraints and reduced hardware complexity.
3Duration of action of moving object
If the time constraint is extended from 1 UI to 1.5 UI, then the settling time margin is increased, but the sampling frequency must be adjusted to maintain data rate
Solution Approach 1:
The patent uses periodic sampling action with two different clock phases: the DFE sampling clock phase for equalization and the DATA sampling clock phase for data extraction. This periodic action allows the system to extend the settling time margin to 1.5 UI while maintaining the required data rate through coordinated sampling at appropriate intervals, resolving the contradiction between settling time and sampling frequency.
Data Source
AI summary
The present disclosure proposes an adaptive non-speculative DFE with an extended time constraint for a PAM-4 receiver and a method for operating the same. An adaptive non-speculative DFE with an extended time constraint for a PAM-4 receiver according to the present disclosure comprises a Continuous-Time Linear Equalizer (CTLE) to boost high-frequency components of an input signal, a Track and Hold (T&H) circuit to track and hold an output of the CTLE, and a sampler, wherein the sampler includes a Decision Feedback Equalization (DFE) sampler to equalize an output of the T&H circuit and sample an output of the T&H circuit in a DFE sampling clock phase; and a DATA sampler to sample a signal equalized by the DFE sampler in a DATA sampling clock phase, wherein the DFE sampling clock phase differs from the DATA sampling clock phase.