Switching Converter Driver Circuit With Adaptive Digital On-Time
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Solution Overview
Problem
Existing DC-DC converters with Pulse Skipping Modulators face challenges in controlling output voltage ripple, especially at low loads, and are prone to noise sensitivity and high static current consumption, making them inefficient and costly for low-power applications.
Innovation Solution
An event-driven digital approach is implemented, using a ring oscillator and counter to modulate the active time of the pulse-width modulated signal, allowing for zero static current consumption and improved adaptability to varying load conditions, while maintaining high immunity to noise and reducing silicon area occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If Pulse Skipping Modulator is used to reduce switching losses at low loads, then efficiency is improved, but output voltage ripple becomes difficult to control
Solution Approach 1:
The patent replaces the traditional analog pulse-skipping modulator with a digital event-driven modulator. The digital approach uses a counter and logic circuitry to generate PWM signals, substituting analog timing mechanisms with digital counting and comparison. This enables precise control of the on-time parameter through digital values while maintaining the pulse-skipping operation mode for low-load efficiency.
Solution Approach 2:
The patent introduces a digital on-time parameter that can be dynamically adjusted based on operating conditions. The event-driven modulator uses a counter that counts clock cycles to generate PWM signals with programmable on-times. This allows the control parameter (on-time duration) to be changed digitally rather than through analog component values, enabling flexible adaptation to different load conditions while maintaining stable output voltage.
2Ease of operation
If traditional analog control is used, then output voltage control is straightforward, but static current consumption increases
Solution Approach 1:
The patent replaces analog control circuits with digital event-driven control logic. The analog comparator and continuous timing circuits are substituted with digital counters, logic gates, and event-triggered control mechanisms. This digital substitution eliminates the need for continuous analog signal processing, thereby reducing static current consumption while maintaining voltage control capability through digital feedback.
Solution Approach 2:
The patent employs periodic clock signals to drive the digital counter and generate PWM outputs. Instead of continuous analog comparison, the system uses discrete periodic clock cycles to advance the counter and trigger events. This periodic digital operation allows the control circuit to remain in a low-power state between clock cycles, significantly reducing static current consumption compared to continuously operating analog circuits.
3Reliability
If higher immunity to noise is achieved through digital approach, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple digital functions into a single integrated event-driven modulator block. The counter, comparator, PWM generation logic, and feedback processing are merged into one cohesive digital circuit module. This consolidation achieves noise immunity through digital processing while avoiding the complexity of separate analog stages, as the entire control function is implemented in a unified digital architecture that can be efficiently laid out and routed on silicon.
Data Source
AI summary
A driver circuit includes an input node to receive an input signal for conversion at the output node of a converter, a driver node to provide to a switching power circuit stage in the converter a pulse-width modulated drive signal having an active time, first and second active time generation paths, and a selector circuit coupled to the first and second active time generation paths. The circuit is operable selectively in a first and a second operational mode wherein the driver node receives the pulse-width modulated drive signal having a first active time value generated in the first active time generation path, or a second active time value generated in the second active time generation path. The second active time generation path includes an active time generator network to provide a second active time value with the second active time value adaptively variable to match the first active time value.