Adaptive Digital PLL Clock Scaling for Jitter and Power Control
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Solution Overview
Problem
Conventional digital PLL devices face issues with increased circuit scale, power consumption, jitter, and tracking time due to varying transmitted clock rates, especially with faster clocks from advancements like Deep Color in HDMI specifications.
Innovation Solution
A digital PLL device structure that includes an operation clock generating unit to frequency-divide or multiply the input clock, an n dividing unit to generate a reference signal, a phase comparing unit to adjust the output clock, and an m dividing unit to control the oscillation frequency, with optional frequency detection and selection units to optimize operation based on input clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the transmitted clock is used directly as the operation clock, then the circuit structure is simple, but when the transmitted clock is fast, the circuit scale increases and power consumption increases significantly
Solution Approach 1:
The patent introduces an operation clock generating unit that dynamically adjusts the operation clock frequency based on the transmitted clock frequency. When the transmitted clock is fast, the operation clock is frequency-divided to reduce the operating frequency of the phase comparing unit and other circuits, thereby reducing power consumption. When the transmitted clock is slow, the operation clock is frequency-multiplied to maintain adequate operating frequency, reducing jitter and tracking time. This dynamic adaptation resolves the contradiction between circuit simplicity and power consumption.
Solution Approach 2:
The patent changes the operating parameter (frequency) of the operation clock based on the input conditions. By using frequency division or multiplication in the operation clock generating unit, the system adapts the operation clock frequency to match the transmitted clock frequency characteristics, thereby controlling power consumption while maintaining circuit functionality.
2Device complexity
If the transmitted clock is used directly as the operation clock, then the circuit structure is simple, but when the transmitted clock is slow, the jitter increases and tracking time increases
Solution Approach 1:
The operation clock generating unit dynamically adjusts the operation clock frequency based on the transmitted clock frequency. When the transmitted clock is slow, the system applies frequency multiplication to boost the operation clock frequency, ensuring that the phase comparing unit and other circuits operate at adequate speeds, thereby reducing jitter and tracking time while maintaining circuit structural simplicity.
Solution Approach 2:
The patent changes the operating parameter (frequency) of the operation clock based on the input conditions. By using frequency multiplication in the operation clock generating unit, the system raises the operation clock frequency when the transmitted clock is slow, improving timing accuracy and reducing jitter without complicating the overall circuit structure.
3Use of energy by stationary object
If frequency division is applied to the transmitted clock to reduce power consumption, then power consumption decreases, but when the transmitted clock is slow, the jitter and tracking time increase
Solution Approach 1:
The operation clock generating unit dynamically selects between frequency division and frequency multiplication based on the transmitted clock frequency characteristics. When the transmitted clock is fast, frequency division is applied to reduce power consumption. When the transmitted clock is slow, frequency multiplication is applied to maintain adequate operating frequency and reduce jitter. This dynamic selection resolves the contradiction between power consumption and reliability.
Solution Approach 2:
The patent changes the operating parameter (frequency) of the operation clock based on the input conditions. By adaptively changing between frequency division and frequency multiplication in the operation clock generating unit, the system optimizes power consumption when the transmitted clock is fast while ensuring adequate performance when the transmitted clock is slow.
4Reliability
If the operation clock frequency is increased to reduce jitter and tracking time, then jitter and tracking time decrease, but circuit scale and power consumption increase
Solution Approach 1:
The operation clock generating unit dynamically adjusts the operation clock frequency based on the transmitted clock frequency. Instead of using a fixed high frequency that would increase power consumption, the system uses frequency multiplication only when necessary (when the transmitted clock is slow), thereby reducing jitter and tracking time only when needed, while avoiding unnecessary power consumption when the transmitted clock is already fast.
Solution Approach 2:
The patent changes the operating parameter (frequency) of the operation clock adaptively based on input conditions. By using frequency multiplication in the operation clock generating unit only when the transmitted clock is slow, the system achieves adequate jitter and tracking time performance without continuously increasing power consumption.
Data Source
AI summary
An input clock dividing unit frequency-divides an input clock, and an input clock multiplying unit frequency-multiplies the input clock. An operation clock selecting unit selects the frequency-divided clock when the input clock is fast and selects the frequency-multiplied clock when the input clock is slow, based on the frequency detection result of frequency detecting unit. The operation clock selecting unit then outputs the selected clock to a phase comparing unit as an operation clock. The phase comparing unit operates according to the frequency-divided or frequency-multiplied clock, and controls an oscillating unit so that the phase difference between a reference signal and a comparison signal becomes zero. The phase of an output clock is thus caused to track the phase of the reference signal.