Adaptive DLL Clock Signaling for Die-to-Die Deskew
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Solution Overview
Problem
Conventional die-to-die communication in electronic systems face challenges with wide delay ranges, process skew, and fast voltage and frequency changes, leading to high latency and cost in clock deskew solutions, especially in 3-D chiplet systems.
Innovation Solution
Adaptive delay-locked loop (DLL) circuitry is employed to align clock signals across devices, dynamically tracking frequency and voltage changes while maintaining low latency and avoiding high-volume manufacturing calibration, using scalable DLL circuitry that adjusts delay cycles to compensate for variable delays due to supply voltages and temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock distribution networks are used in die-to-die communication, then clock signals can be distributed across devices, but wide delay ranges (hundreds of picoseconds) occur due to voltage, process skew, and temperature variations
Solution Approach 1:
The patent implements a delay-locked loop (DLL) that uses feedback mechanisms to continuously monitor and adjust clock signal delays. The DLL compares the phase and frequency of incoming clock signals with local clock signals and dynamically adjusts delay elements to compensate for variations, thereby maintaining synchronization despite wide delay ranges caused by voltage, process, and temperature changes.
Solution Approach 2:
The patent employs dynamic delay adjustment mechanisms within the DLL circuitry that can adapt in real-time to changing operating conditions. The delay elements are continuously tuned based on feedback signals, allowing the system to dynamically compensate for delay variations across different voltage, temperature, and process conditions rather than relying on fixed delay compensation.
2Adaptability or versatility
If Fast Voltage and Frequency (FGV) change is supported in die-to-die communication, then the system can operate across wide frequency ranges (400 MHz to several GHz), but clock deskew becomes more challenging during frequency transitions
Solution Approach 1:
The DLL incorporates phase-frequency detectors that continuously monitor clock signals during frequency transitions and provide feedback to adjust delay elements. This feedback mechanism ensures that clock deskew accuracy is maintained even when the system operates across wide frequency ranges or undergoes rapid frequency changes, as the DLL dynamically adapts to the new frequency conditions.
Solution Approach 2:
The patent implements dynamic delay adjustment mechanisms that can rapidly respond to frequency changes. The DLL circuitry continuously tunes its delay elements based on real-time feedback, allowing it to maintain accurate clock deskew performance during FGV transitions and across the entire operating frequency range from 400 MHz to several GHz.
3Ease of manufacture
If source synchronous communication with asynchronous FIFOs is used, then data can be transmitted between devices, but additional latency is added to latency-sensitive data paths
Solution Approach 1:
The patent removes asynchronous FIFOs from the critical data path by implementing synchronous communication interfaces. This extraction of the FIFO buffering function eliminates the additional latency that FIFOs introduce to latency-sensitive data paths while maintaining the ability to handle clock skew and frequency differences between devices through the DLL-based synchronization approach.
4Reliability
If conventional die-to-die clock deskew solutions are implemented, then clock signals can be aligned across devices, but expensive high-volume manufacturing calibration is required which increases test time and manufacturing cost
Solution Approach 1:
The patent implements self-calibrating DLL circuits that automatically adjust their delay parameters without requiring external calibration equipment or procedures. The DLLs use built-in feedback mechanisms to autonomously optimize clock alignment across devices during normal operation, eliminating the need for expensive high-volume manufacturing calibration processes and reducing both test time and manufacturing costs.
Solution Approach 2:
The patent incorporates preliminary calibration routines that are automatically executed during device initialization or power-up sequences. These preliminary actions pre-adjust the DLL parameters to optimal values before normal operation begins, ensuring accurate clock alignment without requiring subsequent manual or equipment-based calibration during manufacturing or operation.
Data Source
AI summary
Some embodiments include an apparatus having a first delay line of a delay-locked loop (DLL) circuitry, the first delay line including an input node to receive an input clock signal and delay stages coupled in series with the input node; a first multiplexer including input nodes coupled to output nodes of a portion of the delay stages; and a second delay line of the DLL circuitry including an input node coupled to an output node of the multiplexer, and delay stages coupled in series with the input node of the second delay line, the second delay line including an output node to provide an output clock signal.