Adaptive Delay-Locked Loop Clocking for Fast Lock and Low Jitter
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Solution Overview
Problem
Conventional delay-locked loops (DLLs) in semiconductor systems face challenges in reducing locking time and bang-bang jitter while maintaining a loop bandwidth, leading to increased phase differences and operating integrity issues as frequencies increase.
Innovation Solution
A DLL design incorporating a control circuit, delay line, and local clock generator that generates phase control signals to determine lock state and adjust frequency, using a coarse delay line and interpolator to update the phase with varying frequencies and phase variations based on operating modes, allowing for shorter locking times and reduced bang-bang jitter without restricting the loop bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the phase-update frequency is increased during initial locking mode to reduce locking time, then locking time is reduced, but bang-bang jitter increases
Solution Approach 1:
The patent applies dynamics by making the phase-update frequency variable rather than fixed. The frequency is dynamically adjusted based on the locking state: during initial locking mode, a higher phase-update frequency (closer to loop bandwidth) is used to reduce locking time, while during normal locking mode, a lower phase-update frequency is used to reduce bang-bang jitter. This dynamic adaptation resolves the contradiction between locking time and jitter.
Solution Approach 2:
The patent implements periodic action through two distinct operating modes: initial locking mode and normal locking mode. The system periodically switches between these modes based on locking status. During initial locking, coarse phase compensation occurs at high frequency, then transitions to fine phase compensation at lower frequency during normal operation, creating a periodic pattern that addresses both locking time and jitter requirements.
2Loss of time
If the loop bandwidth is extended to allow higher phase-update frequency, then locking time is reduced, but incorrect phase updates may occur
Solution Approach 1:
The patent applies segmentation by dividing the locking process into two distinct phases: initial locking mode and normal locking mode. During initial locking, the phase-update frequency is set closer to the loop bandwidth to enable faster locking. During normal locking, the frequency is reduced to prevent incorrect updates. This segmentation allows the system to benefit from high frequency when needed while avoiding its drawbacks during stable operation.
Solution Approach 2:
The patent changes the phase-update frequency parameter based on operating conditions. During initial locking mode, the frequency is increased toward the loop bandwidth to reduce locking time. During normal locking mode, the frequency is decreased to prevent incorrect phase updates. This parameter adaptation resolves the contradiction between locking speed and update accuracy.
3Productivity
If the operating frequency of the semiconductor circuit is increased, then productivity is improved, but the phase difference increases due to unchanged circuit delay
Solution Approach 1:
The patent uses feedback through the phase detector that continuously monitors the phase difference between the input clock signal and the output clock signal. When operating frequency increases and phase difference grows, the phase detector detects this and generates appropriate phase control signals to adjust the delay line, compensating for the increased phase difference and maintaining synchronization.
Solution Approach 2:
The patent adapts the phase-update frequency parameter in response to operating conditions. When the semiconductor circuit operates at higher frequencies, the DLL adjusts by updating the phase with higher frequency and larger phase variation to compensate for the increased phase difference caused by unchanged circuit delay, thereby maintaining synchronization despite the frequency increase.
Data Source
AI summary
A delay-locked loop (DLL) includes a delay line and a control circuit. The delay line delays an input clock signal based on at least one phase control signal to generate an output clock signal. The at least one phase control signal indicates whether the output clock signal leads or lags the input clock signal. The control circuit generates a division control signal by determining whether the output clock signal is locked with respect to the input clock signal, and generates the at least one phase control signal based on the division control signal. Accordingly, a locking time and bang-bang jitter may be reduced.