Clock Adjustment Circuit With Adaptive DLL Phase Control
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Solution Overview
Problem
Existing semiconductor devices, such as DRAMs, face challenges in efficiently controlling the phase relationship between internal and external clock signals, leading to suboptimal performance and increased power consumption due to intermittent phase adjustment operations.
Innovation Solution
A clock adjustment circuit, including a DLL circuit with a phase comparator and timing generator, is implemented to cyclically assert control signals and adjust the phase difference between clock signals, allowing for intermittent operation based on phase alignment and environmental conditions, thereby reducing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If phase adjustment operations are performed intermittently in existing semiconductor devices, then power consumption is reduced, but phase control precision and performance deteriorate
Solution Approach 1:
The patent implements a feedback mechanism where the timing generator monitors the phase difference between internal and external clock signals and dynamically adjusts the assertion timing of the first control signal based on detected phase alignment. This closed-loop feedback ensures precise phase control while allowing intermittent operation to reduce power consumption.
Solution Approach 2:
The patent makes the timing generator dynamic by allowing it to adaptively change the assertion interval of the first control signal based on environmental conditions and phase alignment detection. The system transitions from fixed intermittent operation to dynamic adaptive operation, maintaining precision while optimizing power consumption.
2Measurement precision
If phase adjustment operations are performed frequently to maintain precision, then phase control precision is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic phase adjustment operations through the timing generator, which asserts the first control signal at optimized intervals rather than continuously or at fixed frequent rates. The periodic action is dynamically adjusted based on phase difference detection, maintaining precision only when necessary and reducing power consumption during stable phase alignment.
3Productivity
If the clock adjustment circuit operates continuously to maintain optimal performance, then performance is improved, but current consumption increases
Solution Approach 1:
The patent makes the DLL circuit operation dynamic by using the timing generator to adaptively control when phase adjustment operations are initiated. The system transitions from continuous operation to dynamic intermittent operation, maintaining optimal performance during phase misalignment while reducing current consumption during stable operation.
Solution Approach 2:
The timing generator autonomously monitors phase alignment and self-determines when to initiate phase adjustment operations without continuous external control. This self-service mechanism allows the circuit to maintain performance when needed while automatically entering low-power states during stable operation.
4Speed
If the assertion interval of the first control signal is shortened to improve phase control, then phase control responsiveness is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic adjustment of the assertion interval for the first control signal through the timing generator. The interval is shortened only when phase misalignment is detected, providing responsive phase control when needed, while being extended during stable operation to reduce power consumption.
Data Source
AI summary
Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.