Adaptive DLL Phase Detection for Jitter-Tolerant Locking
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Solution Overview
Problem
Existing Delay-Locked Loop (DLL) circuits face challenges in maintaining a locked state due to jitter and noise, especially at high-speed operations, where conventional narrow lock-detect windows lead to timing margin issues and increased jitter performance.
Innovation Solution
The implementation of adaptive digital phase detection circuitry that divides both the reference and feedback clocks before reaching the phase-locked state, allowing for a wider lock-detect window and reduced phase detection frequency to maintain lock and improve timing margin, thereby enhancing jitter performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a narrow lock-detect window is used in conventional DLL circuits, then the lock-in time is minimized, but timing margin is reduced and jitter performance deteriorates under noisy conditions
Solution Approach 1:
The patent applies dynamics by making the lock-detect window adaptive rather than fixed. The window width dynamically changes based on the locking state: narrow during acquisition to minimize lock-in time, and wide during maintenance to improve jitter performance. This is achieved through state machine control that adjusts the detection window parameters based on whether the DLL is in lock-acquisition or lock-maintenance mode.
Solution Approach 2:
The patent segments the locking process into distinct phases: lock-acquisition mode and lock-maintenance mode. Each phase uses different lock-detect window configurations optimized for its specific purpose. This segmentation allows the system to use narrow windows during acquisition (fast locking) and wide windows during maintenance (jitter tolerance), resolving the contradiction between speed and reliability.
2Reliability
If the lock-detect window is widened to improve jitter performance, then reliability under noisy conditions is improved, but timing margin is reduced for high-speed operations
Solution Approach 1:
The system dynamically adjusts the lock-detect window width based on operational phase. During lock-acquisition, a narrow window preserves timing margin for high-speed operation. During lock-maintenance, a wide window improves jitter performance. The state machine transitions between modes, automatically selecting the appropriate window width to balance speed and reliability requirements.
Solution Approach 2:
The patent uses preliminary action by establishing the locking state through a narrow window first (acquisition phase), then transitioning to a wide window for maintenance. This preliminary narrow-window detection ensures fast acquisition with adequate timing margin, after which the system can afford to use a wider window for improved jitter tolerance without compromising overall performance.
3Loss of time
If full-rate clocks are used for phase detection before DLL is locked, then lock-in time is minimized, but timing margin becomes insufficient at very high clock speeds
Solution Approach 1:
The system dynamically selects between full-rate and divided clocks based on the locking state. During lock-acquisition, full-rate clocks are used to minimize lock-in time. During lock-maintenance, divided clocks are used to provide adequate timing margin. The state machine controls this dynamic switching, allowing the system to optimize for speed during acquisition and for stability during maintenance.
Solution Approach 2:
The patent applies preliminary action by using full-rate clocks for the initial locking phase to achieve fast acquisition, then transitioning to divided clocks for the maintenance phase. This preliminary use of full-rate clocks establishes the lock quickly, after which the system can switch to the more conservative divided-clock approach that provides sufficient timing margin for high-speed operation.
4Speed
If divided clocks are used for phase detection to provide timing margin, then timing margin is improved, but lock-in time increases due to reduced edge transitions
Solution Approach 1:
The system dynamically switches between full-rate and divided clocks based on the locking phase. During lock-acquisition, full-rate clocks provide maximum edge transitions for fast locking. During lock-maintenance, divided clocks provide adequate timing margin. The state machine orchestrates this dynamic switching, allowing each clock rate to be used in the phase where it is most effective.
Solution Approach 2:
The patent segments the clock usage by function: full-rate clocks are dedicated to the lock-acquisition phase where fast locking is critical, while divided clocks are dedicated to the lock-maintenance phase where timing margin is critical. This functional segmentation allows each clock source to be optimized for its specific purpose without compromise.
Data Source
AI summary
Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.