Adaptive DPLL Bandwidth Control for Low Jitter Tracking
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Solution Overview
Problem
Digital phase locked loop (DPLL) circuits face challenges due to quantization noise introduced by digital phase-frequency detectors and digitally controlled oscillators, which degrade phase noise and jitter performance, and are sensitive to manufacturing processes, especially with smaller transistor features.
Innovation Solution
A digital PLL with a dynamically controllable filter that adjusts bandwidth in response to real-time phase error, using adjustable filter coefficients to maintain low jitter while ensuring sufficient tracking responsiveness, by reducing bandwidth when phase error is low and increasing it when high.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed bandwidth DPLL is used, then the circuit structure is simple, but the jitter and phase noise performance are degraded
Solution Approach 1:
The patent implements dynamic bandwidth adjustment by making the loop filter coefficients adjustable based on operating conditions. The bandwidth is dynamically changed in response to detected signal characteristics, allowing the DPLL to adapt to different scenarios and optimize phase noise and jitter performance while maintaining manageable circuit complexity through structured control mechanisms.
2Speed
If the bandwidth is increased to improve tracking responsiveness, then the tracking performance improves, but the jitter increases
Solution Approach 1:
The patent dynamically adjusts the loop bandwidth based on the tracking requirements and signal conditions. When tracking responsiveness is needed, the bandwidth is increased; when jitter performance is prioritized, the bandwidth is reduced. This dynamic adjustment resolves the contradiction by allowing the system to optimize both tracking speed and jitter performance under different operating conditions.
Solution Approach 2:
The patent changes the loop filter parameters (bandwidth coefficients) based on operating conditions to resolve the trade-off between tracking responsiveness and jitter performance. By adjusting these parameters dynamically, the system can achieve fast tracking when needed while maintaining low jitter during stable operation.
3Measurement precision
If the bandwidth is reduced to decrease jitter, then the jitter performance improves, but the tracking responsiveness decreases
Solution Approach 1:
The patent implements dynamic bandwidth control that reduces the loop bandwidth when jitter performance is the priority and the signal is stable, while maintaining the capability to increase bandwidth when fast tracking is needed. This dynamic approach allows the system to achieve low jitter during normal operation while preserving tracking responsiveness when required.
Data Source
AI summary
In some embodiments, a digital PLL (DPLL) is disclosed with a dynamically controllable filter for changing the effective DPLL bandwidth in response to one or more real-time performance parameters such as phase error.