Adaptive ECC Bypass Control for MLC Memory Error Levels
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Solution Overview
Problem
Existing ECC structures face inefficiencies due to unnecessary complexity, increased latency, power consumption, and reduced code rate when error levels in channels vary, as they often require high-complexity structures for high error levels and simple structures for low error levels, leading to suboptimal performance and resource usage.
Innovation Solution
The proposed solution involves an ECC apparatus and method that dynamically control ECC performance by bypassing portions of ECC blocks based on error levels, using a bypass control signal to determine which ECC blocks to activate or deactivate, thereby reducing complexity, power consumption, and redundant data transmission, and optimizing code rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a concatenated ECC structure is used to correct high error levels, then error correction capability is improved, but device complexity and processing time increase
Solution Approach 1:
The patent implements dynamic selection of ECC processing paths based on real-time channel error levels. A controller determines whether to activate the concatenated ECC structure (high error correction capability but complex) or a simpler single ECC structure (lower capability but simple), allowing the system to adapt its complexity to actual needs rather than always using the most complex structure
Solution Approach 2:
The ECC processing function is segmented into multiple independent paths: a first ECC processing unit for high error correction capability, a second ECC processing unit for lower error correction capability, and a controller that selects which path to use. This segmentation allows the system to use only the necessary processing capability for each specific error condition
2Reliability
If all ECC blocks are used for error correction, then error correction capability is improved, but latency and power consumption increase unnecessarily when error levels are low
Solution Approach 1:
The patent applies partial action by using only the necessary portion of ECC processing capability for each error condition. When error levels are low, the system uses a simplified ECC path with fewer processing blocks. When error levels are high, the full concatenated ECC structure is activated. This ensures that processing resources are not wasted when full capability is not needed
Solution Approach 2:
The system dynamically adjusts the ECC processing path based on real-time error level detection. The controller monitors channel conditions and switches between different ECC processing configurations, allowing latency to be minimized when possible while maintaining sufficient error correction capability when needed
3Reliability
If all ECC blocks are activated, then error correction capability is improved, but power consumption increases unnecessarily when error levels are low
Solution Approach 1:
The patent implements partial action by activating only the necessary ECC processing blocks based on error level. When error levels are low, fewer ECC blocks are activated, reducing power consumption. When error levels are high, more blocks are activated to provide sufficient error correction. This prevents wasteful power consumption when full ECC capability is not required
Solution Approach 2:
The system dynamically controls the activation state of different ECC processing blocks based on real-time error level detection. The controller enables or disables specific ECC processing paths according to channel conditions, allowing power consumption to be optimized while maintaining adequate error correction capability for the actual error conditions present
4Reliability
If a concatenated ECC structure is used, then error correction capability is improved, but code rate is reduced unnecessarily when error levels are low
Solution Approach 1:
The patent applies partial action by using only the necessary ECC processing capability for each error condition. When error levels are low, a simpler ECC structure with higher code rate is used, allowing more data to be transmitted effectively. When error levels are high, the concatenated ECC structure with lower code rate is activated to ensure sufficient error correction. This optimizes the balance between error correction capability and data transmission efficiency
Data Source
AI summary
An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.