Adaptive ECC Interleaving for Latency and Code Rate Balance
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Solution Overview
Problem
Existing ECC systems face inefficiencies due to fixed interleaving levels, leading to increased latency and reduced code rate when error levels change in channels, and require complex circuit configurations to adapt between low and high error levels.
Innovation Solution
An ECC apparatus and method that dynamically control the number of storage elements and ECC performance using an I-interleaved coding scheme based on channel error levels, generating ECC control signals from channel information to optimize encoding and decoding processes, thereby reducing latency and improving code rate while maintaining low complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-level interleaved coding scheme is used to increase error correction capability, then error correction capability is improved, but latency is increased and code rate is decreased
Solution Approach 1:
The patent applies dynamics by making the interleaving level adjustable rather than fixed. The ECC controller dynamically changes the interleaving level based on channel error conditions, allowing the system to use high interleaving levels when errors are frequent (improving reliability) and low interleaving levels when errors are rare (reducing latency and improving code rate).
Solution Approach 2:
The patent changes the parameter of interleaving level based on channel conditions. By monitoring channel error rates and adjusting the interleaving level accordingly, the system optimizes the balance between error correction capability and performance metrics like latency and code rate.
2Reliability
If a high-level interleaved coding scheme is used to increase error correction capability, then error correction capability is improved, but code rate is decreased
Solution Approach 1:
The system dynamically adjusts the interleaving level based on channel error conditions. When channel conditions are good (low error rate), the system uses low interleaving levels, maintaining high code rate and productivity. When channel conditions deteriorate (high error rate), the system increases the interleaving level to improve error correction capability.
Solution Approach 2:
The patent changes the interleaving level parameter in response to channel error rates. This parameter adjustment allows the system to optimize code rate under normal conditions while maintaining sufficient error correction capability when needed.
3Adaptability or versatility
If multiple ECC structures are configured to adapt to different error levels, then adaptability is improved, but device complexity is increased
Solution Approach 1:
The patent implements a universal ECC controller that can operate with different interleaving levels using a single generator polynomial. This multi-functional design allows the system to adapt to different error levels without requiring separate ECC structures for each error condition, thereby maintaining low device complexity while achieving high adaptability.
Solution Approach 2:
Rather than configuring multiple static ECC structures, the patent uses a dynamic approach where a single ECC controller adjusts its operation (interleaving level) based on channel conditions. This eliminates the need for multiple dedicated circuits while maintaining adaptability to varying error levels.
Data Source
AI summary
An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.