Memory Controller ECC Level Selection for Multi-Bit Error Correction
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Solution Overview
Problem
Traditional ECC systems provide limited ECC capability, unable to offer two or more bit error correction, which is necessary for protecting critical system data at high data rates, and are often costly due to the requirement of an additional ECC memory chip and wider interface.
Innovation Solution
A controller that dynamically switches ECC protection levels and reallocates memory device portions to generate and store ECC data, providing stronger ECC capability by using Low-Latency ECC (LL-ECC) and Block-ECC modes, allowing for two or more bit error correction without the need for an additional ECC memory chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC memory devices are used to provide ECC capability, then error detection and correction is enabled, but the system cost increases due to additional memory chips and wider interfaces
Solution Approach 1:
The patent extracts the ECC functionality from a dedicated ECC memory device and implements it within the controller using software-based algorithms. This separates the ECC function from the hardware structure, allowing standard memory devices to provide ECC protection without requiring additional memory chips or wider interfaces, thereby reducing system cost while maintaining reliability
Solution Approach 2:
The patent creates a software copy of the ECC functionality that replicates the error correction capabilities traditionally provided by hardware ECC memory devices. By implementing ECC algorithms in software within the controller, the system achieves the same protective function without the physical overhead of dedicated ECC hardware components
2Reliability
If traditional ECC systems are used, then basic error correction is provided, but two or more bit error correction capability is not achieved
Solution Approach 1:
The patent implements dynamic ECC protection levels that can be adjusted based on system requirements. The controller can switch between different ECC algorithms and protection levels (including single-bit correction, double-bit correction, and detection-only modes) depending on the operational context, enabling the system to adapt its error correction capability to match the actual reliability needs of different workloads
Solution Approach 2:
The patent changes the parameters of ECC protection by implementing multiple configurable ECC levels. Instead of a fixed ECC capability, the system can modify the ECC protection level parameter dynamically, allowing it to provide stronger correction capabilities (2-bit or more) when needed while maintaining flexibility for different operational requirements
3Reliability
If ECC memory devices are used to provide ECC capability, then error protection is enabled, but power consumption increases
Solution Approach 1:
The patent replaces power-hungry hardware ECC components with software-based ECC algorithms running in the controller. This software implementation consumes less power while providing the same error protection function, as it eliminates the need for dedicated ECC memory chips and wider interfaces that increase power consumption
4Reliability
If ECC memory devices are used, then ECC capability is provided, but data throughput may be reduced due to wider interfaces
Solution Approach 1:
The patent extracts the ECC processing function from the memory interface path and places it in the controller. This allows the memory interface to maintain its original width and throughput characteristics while the controller handles ECC generation and verification separately, preventing any degradation in data throughput while still providing robust ECC capability
Data Source
AI summary
A memory controller provides error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to identify an ECC protection level from a plurality of ECC protection levels for data that is to be stored in the memory device, generate ECC data for the data that is to be stored in the memory device using an ECC corresponding to the identified ECC protection level, store the generated ECC data in the cache, and store the data in the memory device.