Adaptive ECC Memory Controller for Aging Nonvolatile Memory
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Solution Overview
Problem
Existing memory technologies face challenges in maintaining error correction capability while minimizing circuit scale and memory size as memory miniaturization increases error probability, leading to inefficiencies in data storage and capacity.
Innovation Solution
A memory controller that dynamically adjusts error correction encoding methods based on the fatigue degree of memory areas, switching to higher capability encodings when degradation exceeds a threshold and ensuring the total parity does not exceed a predetermined amount, thus optimizing error correction without increasing circuit scale or memory size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data size of parity is increased to improve error correction capability, then error correction capability is improved, but circuit scale increases and user data capacity decreases
Solution Approach 1:
The patent applies dynamics by making the error correction capability adjustable rather than fixed. The memory controller dynamically changes the error correction capability according to the fatigue degree of the memory, switching between different correction levels (e.g., single-bit correction vs. double-bit correction) based on real-time memory health status. This resolves the contradiction by allowing the system to use higher error correction capability only when necessary, rather than maintaining maximum capability constantly, thus avoiding unnecessary circuit complexity while ensuring reliability when needed.
Solution Approach 2:
The patent changes the parameter of error correction capability based on the fatigue degree of the memory. When the memory is new or in good condition, a lower error correction capability is used. When the fatigue degree exceeds a threshold, the system switches to a higher error correction capability. This parameter adjustment allows the system to optimize between reliability and circuit scale by matching the error correction level to the actual memory health status.
2Reliability
If the data size of parity is increased to improve error correction capability, then error correction capability is improved, but the capacity of user data to be stored decreases
Solution Approach 1:
The system dynamically adjusts the error correction capability based on memory fatigue degree. When the memory is in good condition, less parity data is used, leaving more capacity for user data. When the fatigue degree increases, the system switches to higher error correction capability, allocating more resources to reliability. This dynamic adjustment resolves the contradiction by ensuring that user data capacity is maximized when reliability concerns are minimal, while still providing adequate error correction when needed.
3Quantity of substance
If memory miniaturization is pursued to increase storage density, then storage capacity increases, but error probability increases
Solution Approach 1:
The patent addresses this contradiction by implementing a dynamic error correction system that adapts to the increased error probability from miniaturization. Instead of using high error correction capability from the start (which would reduce storage capacity), the system begins with lower correction levels to maximize storage density. As memory cells degrade over time due to miniaturization stress, the system detects increased error rates and switches to higher error correction capabilities, thus maintaining both high storage density and adequate reliability throughout the memory lifecycle.
Data Source
AI summary
According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.