Adaptive ECC Control for High-Error Nonvolatile Memory
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Solution Overview
Problem
Nonvolatile memory devices, such as PCRAM, MRAM, NFGM, RRAM, and polymer RAM, face high error rates due to narrow read margins and cell interference, necessitating effective error correction mechanisms to ensure data reliability.
Innovation Solution
A memory system with a test vector generator, data discrepancy checker, and error correction code (ECC) controller that dynamically adjusts ECC levels based on calculated error rates, performing ECC encoding and decoding operations to maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If advanced process techniques and MLC techniques are used to increase integration density, then the number of bits stored per cell increases, but cell-to-cell interference occurs and data errors increase
Solution Approach 1:
The patent changes the parameter of ECC strength dynamically based on detected error rates. When error rates exceed a threshold, the system increases ECC strength to correct more errors, and when error rates are low, it reduces ECC strength to save resources. This adaptive parameter adjustment resolves the contradiction by allowing high integration density while maintaining reliability through dynamic error correction.
Solution Approach 2:
The patent implements a feedback mechanism where the memory controller continuously monitors error rates from read operations and adjusts ECC strength accordingly. The system detects error patterns, compares them against thresholds, and modifies ECC parameters in response, creating a closed-loop control system that maintains data reliability despite high cell density and interference.
2Reliability
If strong ECC schemes are always applied to guarantee reliability, then data error correction capability increases, but processing time and computational resources increase
Solution Approach 1:
The patent makes the ECC strength dynamic rather than static. The system adjusts ECC parameters in real-time based on actual error rates detected during operation. When error rates are low, weaker ECC is applied reducing processing time, and when error rates increase, stronger ECC is activated to maintain reliability. This dynamic adaptation resolves the contradiction between always maintaining high reliability and avoiding excessive processing overhead.
Solution Approach 2:
The system changes ECC parameters (such as code rate, block size, or algorithm complexity) based on detected error conditions. By adjusting these parameters dynamically, the system applies only the necessary error correction strength for current operating conditions, avoiding the constant time and resource overhead of always using the strongest possible ECC scheme.
3Reliability
If ECC strength is increased to handle high error rates, then data reliability improves, but memory access speed decreases
Solution Approach 1:
The patent implements dynamic ECC strength adjustment based on real-time error rate monitoring. When error rates are within acceptable thresholds, the system uses weaker ECC schemes that have minimal impact on access speed. When error rates exceed thresholds, the system strengthens ECC to maintain data integrity. This dynamic approach resolves the contradiction by applying strong ECC only when necessary, rather than always sacrificing speed for reliability.
Solution Approach 2:
The system applies partial ECC strength proportional to the actual error conditions rather than always applying maximum ECC strength. By using just enough error correction capability to handle the detected error rate, the system avoids the excessive processing overhead that would slow down memory access, while still maintaining adequate data integrity when needed.
4Measurement precision
If test vectors are continuously written and read to monitor error rates, then error detection accuracy improves, but memory wear and operational overhead increase
Solution Approach 1:
The patent implements periodic rather than continuous error rate monitoring using test vectors. The system performs error rate measurements at predetermined intervals or under specific conditions (such as after certain numbers of write operations or when error thresholds are approached). This periodic approach maintains adequate error detection accuracy while significantly reducing the frequency of test operations, thereby minimizing additional memory wear and operational overhead.
Solution Approach 2:
The system performs error rate monitoring and ECC strength adjustment as a preliminary action before normal memory operations that could be affected by high error rates. By proactively detecting errors and adjusting ECC parameters in advance, the system maintains data integrity without needing continuous monitoring, reducing both the frequency of test operations and the associated memory wear and overhead.
Data Source
AI summary
A memory system may include a test vector generator configured for generating a test vector to be written into a memory device, a data discrepancy checker configured for comparing read data outputted from the memory device with the test vector to generate an information signal corresponding to a comparison between the read data and the test vector, an error correction code (ECC) controller configured for performing an ECC encoding operation and an ECC decoding operation according to any one among a plurality of ECC levels based on a control signal, and a memory controller controlling the test vector generator, the data discrepancy checker and the ECC controller. The memory controller configured to transmit the control signal corresponding to an error rate of the memory device to the ECC controller, based on the information signal generated by the data discrepancy checker.