Adaptive ECC Selection in Memory Reads to Cut Power Use
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Solution Overview
Problem
Conventional non-volatile memory systems use maximum power for error correction operations on all codewords, even though most only require zero or a small number of correction bits, leading to inefficient power consumption and excessive parity bit switching.
Innovation Solution
A memory apparatus and data accessing method that dynamically select between a first ECC operation and a second ECC operation based on the error bit number of each codeword, using a pre-saved indicator to determine whether to activate a Hamming (12, 8) code or a BCH (50, 32) code for error correction, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one ECC scheme is operated on each codeword, then error correction capability is ensured, but power consumption increases unnecessarily
Solution Approach 1:
The patent implements dynamic selection between different ECC schemes (first ECC and second ECC) based on the actual error condition of each codeword. The system transitions from a static, fixed ECC approach to a dynamic, adaptive approach where the ECC strength is adjusted according to the number of error bits detected in the message bits, thereby optimizing power consumption while maintaining reliability.
Solution Approach 2:
The patent changes the parameter of ECC operation strength by selecting between a first ECC scheme (correcting fewer bits) and a second ECC scheme (correcting more bits). This parameter change is triggered by the indicator value that reflects the error bit number, allowing the system to adapt the correction capability to the actual error condition rather than always using maximum correction strength.
2Reliability
If maximum power is used for ECC operation on every codeword, then all error bits are corrected, but unnecessary power is consumed for codewords with zero or small error bits
Solution Approach 1:
The patent applies partial action by selecting the first ECC scheme (which corrects fewer bits) when the indicator shows that the codeword has zero or small error bits. Instead of always applying the maximum correction capability (second ECC scheme), the system applies only the necessary correction strength based on the actual error condition, thereby avoiding excessive power consumption while maintaining sufficient error correction completeness.
Solution Approach 2:
The patent uses the indicator as feedback information that reflects the error bit number of the message bits. This feedback mechanism allows the system to determine which ECC scheme to apply, creating a closed-loop control where the ECC operation is adjusted based on the actual error condition detected in the codeword.
3Device complexity
If only one ECC scheme is used, then implementation is simple, but parity bits need to switch maximum number of times
Solution Approach 1:
The patent introduces dynamic selection between multiple ECC schemes based on the indicator value, which reduces the frequency of parity bit switching by matching the ECC scheme to the actual error condition. Although the system has multiple ECC schemes available, the dynamic selection based on the indicator ensures that parity bits switch only when necessary, improving productivity compared to a single fixed ECC scheme.
Data Source
AI summary
The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.