Adaptive ECC Decoding for Non-Volatile Memory Read Reliability
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Solution Overview
Problem
Non-volatile memory devices face challenges in error correction when memory cell deterioration is severe, leading to increased latency and reduced reliability due to the limitations of existing error correction codes (ECC) in correcting errors during read operations.
Innovation Solution
A controller and storage device system that includes an error correction circuit capable of selecting an optimal error correction decoding level based on predicted memory cell distribution, using side information from non-volatile memory devices to perform adaptive defense codes, such as on-chip valley search (OVS) operations, to correct errors effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed error correction decoding level is used, then the device complexity is reduced, but the reliability deteriorates when memory cell deterioration is severe
Solution Approach 1:
The patent implements dynamic error correction decoding by selecting different ECC decoding levels (first, second, or third levels) based on the distribution characteristics of memory cells. The controller performs valley search operations to determine the optimal read level and dynamically adjusts the ECC decoding strength accordingly, transforming the static error correction system into an adaptive one that responds to actual memory conditions.
Solution Approach 2:
The system changes the error correction parameters by selecting from multiple ECC decoding levels with different correction capabilities. Based on the predicted memory cell distribution and valley search results, the controller adjusts the decoding level parameter to match the severity of memory deterioration, thereby optimizing both reliability and resource utilization.
2Reliability
If read retry operations with different sensing techniques are performed, then the reliability is improved, but the loss of time increases due to additional operations
Solution Approach 1:
The patent performs valley search operations and distribution prediction as preliminary actions before executing the main error correction decoding. By anticipating the memory cell distribution characteristics and determining the appropriate read level in advance, the system prepares the optimal error correction strategy beforehand, avoiding time-consuming trial-and-error retry operations.
Solution Approach 2:
The system uses feedback from valley search operations and distribution prediction results to dynamically select the error correction decoding level. The controller continuously monitors memory conditions through side information and adjusts the ECC decoding strategy based on this feedback, enabling adaptive error correction that responds to actual memory state without requiring multiple fixed retry attempts.
Data Source
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AI summary
A controller (400) including a non-volatile memory interface circuit (460) connected to at least one non-volatile memory device (300) and configured to control the at least one non-volatile memory device (300); an error correction circuit (430) configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit (460) according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit (460) is further configured to: receive side information from the at least one non-volatile memory device (300); predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.