Adaptive ECC Decoding for MLC Flash Write Error Mitigation
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Solution Overview
Problem
Multi-level cell (MLC) flash memories face challenges in mitigating write errors due to the independent encoding and decoding of least significant bit (LSB) and most significant bit (MSB) pages, which can lead to misplacement of final states and increased write errors, especially when high write throughput is prioritized over error correction.
Innovation Solution
Implementing an adaptive error correction code (ECC) decoder that uses a two-step programming process, where a fast ECC decoder is applied during the write process for LSB pages and a more aggressive ECC decoder is used after both pages are written, aided by side information to balance latency with fidelity and reduce write errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If independent encoding and writing of LSB and MSB pages is used, then write throughput is improved, but write error rate increases
Solution Approach 1:
The patent segments the ECC decoding process into two distinct stages: a fast rough decoder applied independently to LSB pages during writing, and a more comprehensive decoder applied to both LSB and MSB pages after completion. This segmentation allows the system to maintain high write throughput through fast independent LSB decoding while ultimately achieving better error correction through the second-stage joint decoding process.
Solution Approach 2:
The patent applies preliminary ECC decoding to the LSB page immediately after writing, before the MSB page is written. This preliminary action uses a fast rough decoder to quickly identify and correct obvious errors in the LSB page, enabling the system to proceed with MSB writing without waiting for complete joint decoding, thus maintaining high throughput while improving reliability.
2Object-affected harmful factors
If two-step programming process is employed, then cell-to-cell interference is reduced, but write latency increases
Solution Approach 1:
The patent dynamically adjusts the decoding strength applied at different stages: using a fast rough decoder with fewer iterations for LSB pages during the first programming step, and applying a more comprehensive decoder with additional iterations for the second programming step. This dynamic adaptation allows the system to minimize latency during critical path operations while still achieving thorough error correction.
Solution Approach 2:
The patent changes the decoding parameters (number of iterations, decoding complexity) based on the programming stage. During the first programming step, a fast decoder with minimal iterations is used to quickly process LSB pages. During the second programming step, the decoder is applied again with increased iterations to correct any remaining errors, thus balancing latency and interference reduction.
3Productivity
If fast ECC decoding is used during write process, then write throughput is maintained, but error correction fidelity decreases
Solution Approach 1:
The patent segments the ECC decoding into two phases: a fast rough decoding phase applied during writing that maintains throughput, and a second comprehensive decoding phase applied after writing that enhances fidelity. The segmentation allows each phase to be optimized for its specific purpose without compromise.
Solution Approach 2:
The patent applies ECC decoding continuously across both programming steps rather than performing a single comprehensive decoding only at the end. The fast rough decoder is applied immediately after LSB writing, and the comprehensive decoder is applied after MSB writing, ensuring continuous error correction action that maintains both throughput and fidelity.
Data Source
AI summary
An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.