Adaptive Data Encoding Circuit Without Clock Signal Distribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional data transmission techniques in microprocessors suffer from high power consumption due to voltage transitions and require clock signal distribution, leading to inefficiencies in bandwidth and power management, especially as processor sizes increase and in scenarios like static screen displays or BlueRay playback where power needs to be minimized.
Innovation Solution
A method of transmitting data using a waveform with signal transitions on a subset of wires, where the receiver measures the duration between transitions using a locally generated clock signal, allowing for efficient data encoding and reduced power consumption independent of data values, eliminating the need for clock signal distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional parallel transmission techniques are used to transmit data, then data transmission speed is improved, but power consumption increases due to multiple voltage transitions on multiple wires
Solution Approach 1:
The data transmission is segmented into multiple phases where only one wire is active at a time. The N-bit data is divided and transmitted sequentially across different time slots on different wires, rather than transmitting all bits simultaneously. This segmentation reduces the number of concurrent voltage transitions from N to 1, significantly reducing power consumption while maintaining data transmission capability.
Solution Approach 2:
The transmission scheme uses periodic time-multiplexed action where each wire is activated in sequence for specific time slots. Data bits are transmitted periodically across different wires in a round-robin fashion, ensuring that only one wire undergoes voltage transition at any given moment. This periodic activation pattern reduces interconnect power consumption while completing the full data transmission over the periodic cycle.
2Use of energy by moving object
If conventional deterministic PPM transmission is used, then power consumption becomes independent of data values, but bandwidth efficiency decreases and clock distribution is required
Solution Approach 1:
The invention adds the time dimension to the transmission scheme by using time-multiplexed sequential transmission. Instead of transmitting all data bits simultaneously in parallel (spatial dimension only), the system uses both spatial (multiple wires) and temporal (time slots) dimensions. Each wire is assigned specific time slots, creating a two-dimensional transmission matrix that improves bandwidth utilization while maintaining deterministic power consumption characteristics.
Solution Approach 2:
The transmission scheme dynamically assigns wires to different data bits based on the data pattern being transmitted. The system adapts which wire is activated in each time slot based on the specific data values, optimizing the use of available transmission channels. This dynamic wire assignment improves bandwidth efficiency compared to static PPM while preserving the benefit of data-independent power consumption.
3Reliability
If clock signal distribution is implemented for synchronization, then transmitter and receiver synchronization is improved, but power consumption and system complexity increase
Solution Approach 1:
The receiver is designed to self-synchronize with the transmitter by detecting the periodic transmission pattern and time slots autonomously. Instead of relying on external clock signals from the transmitter, the receiver independently identifies the transmission rhythm and aligns its sampling accordingly. This self-service synchronization mechanism eliminates the need for clock distribution infrastructure and associated power consumption while maintaining reliable data reception.
Solution Approach 2:
The clock signal distribution function is extracted and removed from the system. Rather than having the transmitter generate and distribute clock signals to the receiver, the clock synchronization function is taken out and replaced by the receiver's autonomous time-slot detection capability. This extraction eliminates the clock tree infrastructure and its power consumption while preserving synchronization reliability.
4Adaptability or versatility
If interconnect length is increased to accommodate larger processor sizes, then processor capacity is improved, but power consumption due to capacitive effects increases
Solution Approach 1:
The data transmission path is segmented into multiple shorter sequential segments using time-multiplexed wire activation. Instead of transmitting data across long parallel interconnects simultaneously, the system breaks down the transmission into multiple time slots where data is sent sequentially over the same physical wires. This segmentation reduces the capacitive loading effects that scale with interconnect length, as only one wire is actively driven at a time despite the physical distance.
Data Source
AI summary
Various energy efficient data encoding schemes and computing devices are disclosed. In one aspect, a method of transmitting data from a transmitter to a receiver connected by plural wires is provided. The method includes sending from the transmitter on at least one but not all of the wires a first wave form that has first and second signal transitions. The receiver receives the first waveform and measures a first duration between the first and second signal transitions using a locally generated clock signal not received from the transmitter. The first duration is indicative of a first particular data value.