Adaptive Envelope Detector for NFC Signal Edge Detection
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Solution Overview
Problem
Conventional envelope demodulators for NFC signals suffer from non-monotonic glitches, distortion, and large chip area occupancy, making precise detection of envelope edges challenging, which is critical for accurate data demodulation and compliance with timing specifications like ISO 14443.
Innovation Solution
An adaptive envelope detector with adaptive threshold decision, comprising a clock extracting device and an edge detecting device, which uses a clock signal and delayed clock signal along with biasing voltages to accurately detect falling and rising edges of NFC signals, overcoming issues like ripple effects and distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a rectifier based envelope demodulator is used to extract the envelope of the NFC signal, then the envelope can be output, but non-monotonic glitches and distortion appear due to capacitor discharging effect and diode nonlinear behavior
Solution Approach 1:
The patent extracts the clock signal from the received NFC signal and uses it to control the sampling timing, separating the envelope detection function from the traditional rectifier-based approach. This extraction method eliminates the harmful effects of capacitor discharging and diode nonlinearities by using a different detection mechanism that samples the signal at precise clock edges.
Solution Approach 2:
The patent replaces the mechanical/electrical rectifier-based envelope detection system with a digital sampling-based system. Instead of using analog components like diodes and capacitors that introduce nonlinearities, the invention uses digital signal processing with precise clock synchronization to detect envelope edges, thereby eliminating the harmful effects of the analog rectification process.
2Stability of the object's composition
If an RC circuit is used in the conventional envelope demodulator, then the envelope can be smoothed, but the RC circuit occupies a large chip area
Solution Approach 1:
The patent replaces the physical RC circuit with a digital filtering and sampling approach. Instead of using large analog components to smooth the envelope, the invention uses digital signal processing techniques that achieve envelope smoothing with minimal chip area, as digital filters can be implemented efficiently in integrated circuits without requiring large physical components.
Solution Approach 2:
The patent changes the operating parameters by using clock-synchronized sampling instead of continuous analog filtering. By sampling the signal at precise intervals determined by the extracted clock signal, the system achieves envelope detection and smoothing without requiring large RC time constants, thereby reducing chip area while maintaining stability.
3Measurement precision
If the time constant of the RC circuit is adjusted to reduce ripple effect, then the ripple effect is reduced, but the negative clipping effect increases
Solution Approach 1:
The patent replaces the RC circuit-based ripple reduction mechanism with a digital sampling approach synchronized to the extracted clock signal. This substitution eliminates the trade-off between ripple reduction and clipping effect because the digital sampling method detects envelope edges at precise timing points without the analog filtering effects that cause negative clipping, thereby achieving ripple reduction without introducing distortion.
Data Source
AI summary
An envelope extracting apparatus includes: a clock extracting device arranged to extract a clock signal of a receiving modulation signal according to a first biasing voltage; and an edge detecting device arranged to generate a detecting signal to indicate an envelope edge of the receiving modulation signal according to a delayed clock signal of the clock signal and a second biasing voltage.