Adaptive Input Equalization for Data Recovery Eye Optimization
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Solution Overview
Problem
Modern digital data communication systems face challenges in recovering clock signals and digital data from serial data signals, particularly in systems without explicit clock signals, leading to errors due to frequency misalignment and signal deviations, which result in increased bit error rates and require periodic reacquisition of the clock signal.
Innovation Solution
A unit within the communication system employs a pattern matching scheme to filter offset and time-delayed samples, utilizing an adaptive equalization amplifier with an inductively peaked cascode stage to set tap values, and includes circuitry for comparing data recovery outputs to adjust tap values based on bit error rates, thereby improving sampling node eye quality and reducing bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase locked loop (PLL) is used to determine clock signal and sample data, then clock recovery is achieved, but frequency misalignment and signal deviations cause increased bit error rates
Solution Approach 1:
The patent applies preliminary action by performing adaptive equalization on the data signal before sampling. The equalizer adjusts tap weights in advance to compensate for anticipated signal distortions and frequency misalignments, ensuring that when the PLL samples the equalized signal, the sampling accuracy is maximized despite initial frequency deviations. This preprocessing step reduces bit error rates by preparing the signal optimally for subsequent sampling operations.
2Productivity
If sampling is performed at fixed intervals without explicit clock demarcation, then bandwidth is increased, but frequency misalignment leads to sampling errors
Solution Approach 1:
The patent applies dynamics by making the sampling system adaptive rather than fixed. The equalizer continuously adjusts its tap weights based on incoming signal characteristics, allowing the sampling system to dynamically compensate for frequency misalignments and signal distortions. This dynamic adaptation enables accurate data recovery even when sampling at fixed intervals without explicit clock demarcation, maintaining both high bandwidth efficiency and reliable data recovery.
3Measurement precision
If periodic reacquisition of clock signal is performed to correct frequency misalignment, then clock accuracy is maintained, but system continuity is disrupted
Solution Approach 1:
The patent applies feedback by using the equalizer to continuously monitor and compensate for frequency misalignments in real-time. Instead of periodic reacquisition that disrupts continuity, the equalizer provides continuous feedback adjustment of tap weights to track and compensate for frequency drift. This continuous feedback mechanism maintains clock frequency accuracy while preserving system continuity, as the equalization process operates seamlessly without requiring reacquisition events.
Data Source
AI summary
Data receivers often include equalizers for operating on received signals. The equalizers often have a plurality of taps, with signals from each tap weighted based on tap settings or values. The tap settings may be set based on bit error rates of data output from the equalizer. In some embodiments data output from the equalizer is split into two signals, and the two signals are processed to indicate a data eye of the data output from the equalizer. Preferred tap settings may be determined by setting tap settings to different values and using tap settings expected to maximize the data eye. This may be performed separately for different bit settings in an attempt to reduce effects of inter-signal interference.